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Google Memory Layout Design Engineer India, Karnataka, Bengaluru 256683839
17.07.2024
Minimum qualifications:
Preferred qualifications:
- Bachelor’s degree in VLSI/Computer Engineering or equivalent practical experience.
- 2 years of experience designing and drawing layout of high-speed/low power memories.
- Experience with developing memory array layout (Row decoders, Write drivers, Assist circuits, Sense Amplifiers, Memory Control circuit) in 3nm (or equivalent) technology node.
- Experience with integrating various blocks of memory array and integrating memory array at SoC level.
Preferred qualifications:
- Master's degree in VLSI/Computer Engineering, or a related field.
- Experience drawing layout for Sense Amplifier, Decoders, Assist Circuits, Latches, Flip-Flops, Isolation Cells, Power Switches, and Level Shifters.
- Experience with placement, track planning, and integration of various blocks within SRAM memories.
- Experience with Virtuoso XL and extraction tools such as Star-RC/QFS.
- Understanding of layout design rules, layout dependent effects, and DFM in FinFET technology nodes.
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