Intel IP Design Engineer/Lead 

India, Karnataka, Bengaluru 

255274458

Job Description:
Creates quality Pre-Silicon Validation collaterals using UVM System Verilog/SystemC and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals for validation readiness. Defines and develops new capabilities and HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-silicon and post-silicon functional and performance validation as well as SWJob Experience:
Technical experience in verification of RTL-based digital systems with very good understating of various system level flows
Experience leading development of verification architecture based on evolving requirement from IP/SOC customers
Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog/SystemC based verification techniques.
Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environments
Experience in SWand debug such as C, C++, Perl, Python
Work experience creating a self-checking emulation/simulation test bench
Highly proficient in UVM techniques for verification
Hands-on experience of emulation and simulation BFM based verification
Good understanding of architectural designdocuments, integration documents)
Preferably good understanding of emulation/simulation platform with major vendors (Synopsys, cadence )
Protocol knowledge : PCIE, CXL, UCIe, CHI, DDRHighly proficient with coherent, non-coherent and concurrent traffic validation
Experience with emulation based systems such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic Veloce
Experience in building emulation based models for large scale designs is a plusJob Responsibilities:
Should be able to review the IP teams requirements, come up with verification plan, test plan, micro-arch, identify scenarios and design intent and develop verification strategies which can ensure defect free IP's
Maintain generic emulation-based verification environment and regression setups for various IP's
Leads activities driving the development of various stimulus to support the emulation based verification of various IP's
Develop and maintain UVM environments for IP interfaces