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Google Chassis Power Architect Device Services Silicon India, Karnataka, Bengaluru 234381940
18.09.2024
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in power optimization workflow and techniques.
- Experience with power management IPs.
Preferred qualifications:
- Experience in low power design including UPF/CPF, multi-voltage domains, power gating, and on chip power management IP design.
- Experience in Verilog, SystemVerilog, RTL and gate-level SPICE simulations, and statistical SPICE models.
- Experience using EDA tools like Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS.
- Experience in post-silicon power calibrations and debug.
- Experience in design and analysis of full chip power with a solid understanding of clock, reset, and power sequencing interactions.
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