IBM Logic Design Engineer 

India, Karnataka, Bengaluru 

224491648

Required Technical and Professional Expertise

• 9 + years of experience in Functional Verification of processors or ASICs.
• Minimum 6+ years of experience in any of the following

• Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification.
• Core architecture/micro-architecture verification
• Multi-processor cache coherency, Memory subsystem verification.
• IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc
• AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification.
• Gate level simulation and emulation.

• Track record in leading team.
• Clock domain crossing and reset domain crossing verification
• Knowledge of functional verification methodology – UVM/OVM/System Verilog/SystemC/
• Knowledge of HDLs (Verilog, VHDL)
• Developed test-plans and test strategies for IP/unit/block level verification.
• Good object-oriented programming skills in C/C++, scripting languages like Python/Perl.
• Worked on multiple levels of verification (unit/element/sub-system/system level)
• Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow
• Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails
• Experience in driving verification coverage closure.

Preferred Technical and Professional Expertise

• Stress testing and ability to identify corner case scenarios.
• Knowledge of high-speed SERDES and PHY Verification
• Good understanding of computer system architecture and microarchitecture.
• Knowledge in IP Integration and SoC level verification.