המקום בו המומחים והחברות הטובות ביותר נפגשים
In this position, you will be encouraged to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.
doing:
Own micro-architecture and RTL development of design modules.
Micro-architect features to meet performance, power and area requirements.
Work with HW architects to define critical features.
Collaborate with verification teams to verify the correctness of implemented features.
Interact with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.
Co-operate with FPGA and S/W teams to prototype the design and ensure that S/W is tested.
Work on post-silicon verification and debug.
see:
BS / MS or equivalent experience.
5+ years of design experience.
Experience in micro-architecture and RTL development of complex designs.
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping,, timing analysis, floor-planning, ECO, bring-up & lab debug.
Expertise in Verilog.
crowd:
Design experience in memory subsystem or network interconnect IP.
Good debugging and problem solving skills.
Scripting knowledge (Python/Perl/shell).
Good interpersonal skills and ability & desire to work as a part of a team.
משרות נוספות שיכולות לעניין אותך