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Cisco Account Manager India, Delhi, New Delhi 223389312
29.04.2025
The application window is expected to close on: 6/10/25
This role will be based out of our San Jose, CA office.
Your Impact:
You are a hard-working, motivated ASIC verification engineer who will be joining our team and contributing to the verification of very complex ASICs. You will have a Design Verification background, in-depth experience in System Verilog and UVM methodology, with experience working in C++, scripting, as well as ASIC design and verification flow.
- Defining and building UVM/SystemVerilog testbenches from scratch or enhancing existing testbenches with focus on reuse.
- Defining new DV methodologies.
- End-to-end verification of one or more design blocks simultaneously while helping the full chip team with integration and support.
- Test plan generation, review, planning, and execution meeting all criteria of the ASIC group.
- Help develop emulation infrastructure using C/C++ that works with UVM based verification environments.
- Gate level simulation and SDF back annotation for blocks as part of pre-silicon verification.
- Code and Functional coverage based simulation runs, coverage collections, merging, and working with designers to fill coverage holes.
- Participating in all phases during ASIC development – RTL verification, emulation, and post-silicon validation.
- Recommending standard methodology, identifying and suggesting innovative solutions for improvements, efficiency, and quality.
- Leading and mentoring a team of junior engineers in addition to the work you're doing.
Minimum Qualifications:
- Bachelor’s degree +8 years of related experience, or Master’s degree +6 years of related experience.
- Demonstrated experience in C/C++ and debugging skills, with experience in System Verilog and UVM methodology
- Prior experience with developing UVM based infrastructure from scratch.
- Ability to handle complex features/parts of a chip independently.
- Proficient in merging and analyzing code coverage data that is generated by functional simulation
Preferred Qualifications:
- The ability to work in a dynamic environment delivering quality work on a tight schedule.
- Ability to build, lead, and mentor a team of engineers, and ensure quality delivery as a team.
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