What you’ll be doing:
Work on structural and functional verification of low power aspects of NVIDIA’s family of smartNICs and DPUs.
Come up with test plans and coverage plans of these features.
Write test cases, test bench components like assertions and coverage points, and own verification convergence.
Collaborate with system level and unit level teams to cover the features well from functional, electrical, performance, and noise aspects.
Be responsible for debugging waves to analyse power consumed by unit IP’s.
Work with architects, designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.
Validate/Correlate the effectiveness of the low power features on silicon.
What we need to see:
BS/MS or equivalent experience with specialisation related to Low Power techniques and Verification.
5+ years of experience.
Fundamental understanding of power basics including transistor-level leakage/dynamic characteristics of VLSI circuits.
Knowledge of power intent formats - UPF/CPF.
Experience in Static Power check - tools like VCLP/MVRC or similar.
Hands-on knowledge in Power aware dynamic verification - NLP/MVSIM or similar tools.
Experience in design and verification tools (VCS, XCelium or equivalent simulation tools, Verdi, Indago or other debug tools).
Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS).
Exposure toCluster/Sub-system/Fullchip/SOClevelverification environments
Ways to stand out from the crowd:
Prior experience of SmartNICs (or DPU) and/or high-speed interconnects.
Good software programming skills. Python/Perl/C++ preferred.
Confident debugging and problem-solving skills.
Good interpersonal skills and ability & desire to work as an excellent teammate.
משרות נוספות שיכולות לעניין אותך