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What you'll be doing:
You will be part of the groundbreaking "Layout Methodology" team with a charter to speed up layout creation, productivity and improve time to market of Nvidia digital IP like SRAM layouts and other custom layout blocks.
Be the first to conduct an in-depth study of new technology and enable the rest of the design teams to seamlessly start off on new/advanced layout technology.
Responsible for creating digital IP to enable layout work in new technology: PCELL creation, SRAM leaf cells, Productivity Scripts.
Responsible for analysis of new technology and translating into guidelines for EMIR, DFM, SRAM layout guidelines etc.
Investigate next generation tools for layout creation.
Investigate the applications of Machine Learning / Deep Learning techniques for layout creation.
What we need to see:
BE/M-Tech in Electrical & Electronics or equivalent experience.
4+ years of experience.
Proven project cycle and tape out experience in SRAM memory layout design.
Experience in advanced technology nodes like 5 or 3 nanometers is a must.
Solid proficiency / expertise in the Cadence Skill language is a requirement for this job.
Experience with pCell development is a big plus.
Solid scripting skills in Python, Perl, Shell is a requirement.
Experience with Deep Learning or Machine Learning tools, Software will be a massive plus for this job and experience with EMIR tools is a big plus, ability to root cause and fix EMIR issues is a requirement.
Good social skills and be an excellent teammate.
Excellent presentation and influencing skills and ability to communicate new ideas/tools to other groups.
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