Cisco ASIC Design Verification Engineer 

China, Shanghai 

186072326

Who You'll Work With

What You'll Do

1. Design and implement complex ASICs.

2. Participate in the architecture definition, implementation and verification phases for our products.

3. Help create detailed design specifications and test plans.

4. Design and implement block level RTL, perform synthesis and achieve timing closure goal.

5. Develop test benches and create test cases

6. Work with cross-functional teams (hardware, software, diagnostics and signal integrity).

7. Assist in complex subsystem level lab bring-up, integration, and unit test verification.

8. China customer enablement on pre-sales, system development, SDK/ASIC validation.

Who You Are

Minimum Qualifications

1. Knowledge on UVM, Verilog, System Verilog, C, C++

2. Skillful at utilizing Verilog/System Verilog in complex logic designs

3. Able to create clean code, using the best practices of software design

4. Proficient in both written and verbal English.

5. Self-motivation, teamwork and strong communication skills are essential

6. Master of EE/CS or related field.

Preferred Qualifications

1. Knowledge of Unix and a scripting tool is a plus

2. Knowledge on networking

3. Knowledge in Digital Communication and Signal Processing

4. Experience in Modem design

5. Knowledge on Mentor Veloce or Cadence Palladium is a strong plus

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