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Google Design Testability Engineer Silicon India, Karnataka, Bengaluru 180208215
Today
Minimum qualifications:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test including silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing.
- Experience with ATPG, Low Value (LV), Built-in self test
(BIST) or Joint Test Action Group (JTAG) tool and flow.
- Experience with a programming language like Perl with Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC) and DFT timing and Static Timing Analysis (STA).
- Knowledge of performance design DFT techniques.
- Knowledge of the end to end flows in Design, Verification, DFT and Partner Domains (PD).
- Ability to scale DFT.
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