Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience in architecture, hardware, digital design, and software co-design
3 years of experience in Verilog/SystemVerilog.
Experience in computer architecture and digital design or Internet Protocol (IP) integration (e.g., Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR) memory).
Preferred qualifications:
Master's degree in Electrical Engineering, Computer Science, or a related field.
4 years of experience working on Field Programmable Gate Array (FPGA) platforms or Emulation platforms with Internet Protocols (IPs) (e.g., Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR) memory, Gigabit Ethernet, Flash).
Experience in developing architectures for Machine Learning Accelerators.
Experience in writing or debugging Verilog/Register-Transfer Level (RTL) code for ASIC/FPGA designs, waveform debug skills with knowledge of chip design flows.