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Google RTL Design Engineer Core-IP Silicon India, Karnataka, Bengaluru 164089449
22.07.2025
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
- Experience in design and development of Security or Audio blocks.
- Experience with a scripting language like Perl or Python.
- Experience with DSI2 or MIPI C/D Phy.
Preferred qualifications:
- Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
- Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.
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