Bachelor's degree in Electrical Engineering or equivalent practical experience.
4 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.
Experience in verification and debug of IP/subsystem/SoCs in the Networking domain such as packet processing, bandwidth management, congestion control desired.
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
Preferred qualifications:
Master's degree in Electrical Engineering or a related field.
Experience with industry-standard simulators, revision control systems, and regression systems.
Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units.
Experience with the full verification life cycle.
Excellent problem-solving and communication skills.