Microsoft Senior Silicon Engineer PD CAD Signoff 

United States, California, Mountain View 

162696685

If you are like tackling complex Register Transfer Logic (RTL) /Implementation challenges and have a keen interest in driving the associatedfor large and intricate digital System on Chip (SoC), this is the perfect place for you! You will be part of a team thatis responsible for

Required Qualifications

• 7+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 5+ years of experience in industry-standard tools such as Cadence Conformal and Synopsys Formality.
• 5+ years of experience with Synthesis tools like Design Compiler, Fusion Compiler, and Genus.
• 5+ years of programming experience in one or more of the following languages: TCL, Python, Perl, SQL, UNIX bash/Makefile

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Ability to debug complex RTL->Synthesis Netlist verification issues and recommend best practices for RTL coding and Synthesis optimization.
• Understanding of Multi-Bit register mapping, Register Merging, Register Retiming, and Clock Gating techniques.
• Familiarity with guidance formats like .svf/.vsdc and associated translation.
• Knowledge of UPF/Power intent specifications and Power State Table (PST) handling.
• Experience in hierarchical modelling for Logical Equivalence closure.
• Experience in developing efficient Logical Equivalence checking flows that support hundreds of end-users.
• Excellent Communication skills across the board
• DFT methodology and handling DFT constraints for Logical Equivalence
• Timing Constraints/Low Power Static verification flows to augment pure functional equivalence.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

• Establish Logical Equivalence Checking (LEC)/Formal Equivalence Verification (FEV) methodology for hierarchical and block-level partitions between RTL, Design for Testability (DFT)-inserted RTL and Gate-level/Power-Ground (PG) Connected netlists on Microsoft’s next-generation large and complex SoCs.
• Enhance design productivity with advanced scripting skills for development/maintenance of large CAD (Computer Aided Design) flow systems
• Perform detailed debug/analysis to guide the RTL and physical design teams across Microsoft’s silicon portfolio in addressing and solving challenging logical equivalence failures.
• Perform cross-functional decision making across UPF (Unified Power Format)/Low Power methodology/architecture, DFT methodology, Synthesis, Place and Route and Extracted Timing model generation in Timing Analysis tools to embellish Logical Equivalence modelling.
• Contribute to raising the standard by discovering innovative synthesis/optimization strategies for optimal power, performance, area and yield without overloading the Logical Equivalence Solver algorithms.
• Implement automatic Functional Engineering Change Order (ECO) methods pre-/post-mask to generate faster, well-optimized, and functionally equivalent patch files.
• Collaborate closely with the EDA partners to identify and deliver the best and most advanced solutions for effective Logical Equivalence closure while optimizing runtimes.
• Embody our and