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QT Technologies Ireland Limited
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
About The Role
You will have experience of Physical Design (PD) flows specifically experience of bringing a design through the full PD flow from netlist to GDS (Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization and DRC closure)
• Understanding of Floor planning, Placement, CTS, P&R
• Experience using different techniques for low power designs and UPF/CPF flows.
• Good understanding of Primetime STA tool and timing closure methodologies.
• Developing and implementing timing ECOs including effect on congestion/routing/power.
• Understanding of different power grid structure, clock tree, and low-power reduction implementation methods.
• Understanding of signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing.
• Understanding of Physical Verification, IR drop analysis, Formal Verification
• Experience in automation using Perl/Python and tcl and ability to develop/support flows related to floor planning, integration and design validation.
• Good communication skills and ability & desire to work in a cross-site cross-functional team environment.
• Experience using Physical Design tools from at least one of the following EDA tool vendors in advanced process nodes, Synopsys (ICC2/Fusion Compiler) or Cadence (Innovus).
• Experience using synthesis tools from at least one of the following EDA tool vendors in advanced process nodes, Synopsys (DC/Fusion Compiler) or Cadence (Genus).
Education & Experience
Bachelor's degree in Science, Engineering, or related field.
• 5+ years ASIC design, verification, or related work experience.
What's on Offer
Apart from working in an open, relaxed and collaborative space, you will enjoy:
Salary, stock and performance related bonus
Maternity/Paternity Leave
Employee stock purchase scheme
Matching pension scheme
Education Assistance
Relocation and immigration support (if needed)
Life, Medical, Income and Travel Insurance
Subsidised memberships for physical and mental well-being
Bicycle purchase scheme
Employee run clubs, including, running, football, chess, badminton + many more
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field.
*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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