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In Q4 2023, Intel announced PSG will be reported as a separate business unit beginning on January 1, 2024 with ongoing support from Intel. This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future with an anticipated target of Jan 1, 2025. We are a leading global semiconductor company at the forefront of innovation, delivering cutting-edge solutions for a diverse range of industries.
Key player in the Yield improvement workgroup, responsible for driving FPGA product yield and product health activities while ensuring new FPGA products are transferred to factory for high volume manufacturing (HVM) ramp.
Ensure the testability and manufacturability of FPGA products with specific emphasis on yield analysis to meet both quality and cost requirement.
Proactively investigate and debug complex test and Si material related yield issues.
Analyse and evaluate component performance to ensure optimal match of component requirements with production equipment capability.
Come up with innovative solutions.
Define the backend product yield roadmap and follow through with execution per project milestones.
Although the key focus areas of this position involve investigating product yield issues, identifying root-cause and delivering solutions, the yield engineer also works closely with a wide range of partners and stakeholders across multiple organization, including Product Development, Process Development, Design, Sort, Test Equipment engineers, labs and Manufacturing teams in order to deliver a high-quality technology for HVM (High Volume Manufacturing).
Demonstrate strong ability in DOE, data collection and analysis using POR Intel (SQLPF, CrystallBall, Aqua etc) or commercial tools (SQL Management Studio etc)
Apply engineering analysis tools (JMP, Excel, etc.) to perform data analysis, yield characterization, commonality analysis, and champion data-driven solution/decision making.
Establish and deliver yield/Product Health improvement roadmaps through Yield Improvement workgroup.
Have in-depth knowledge of Intel Testing methodology and HVM testing environment
Partner with test content owners to analyse and resolve yield limiters
Work closely with FSM (Fab SORT Manufacturing) and TD on incoming materials quality indicators, test conditions and yield correlation to backend
Collaborate with business groups and cross-site partners (e.g. Assembly Test Manufacturing, Fab, Design) to accomplish high quality and cost-effective Yield goals for HVM
BS/MS in Electrical Engineering or equivalent, with at least 5 years of industry experience in IC Design, IC Test, or equivalent field.
Understanding of test methodology for ASIC, SOC and/or FPGAs.
Knowledgeable in digital and analog circuit
Strong demonstrated analytical and problem-solving skills and well versed in test industry trends and technology.
Self-motivated, with proven collaboration and leadership skills
Sound knowledge inIntelmanufacturing and test methodologies in an added advantage
Hands-on experience in manufacturing testing (ATE, debugging, TP, etc.) will be an added advantage
High proficiency in commercialanalytic/visualizationtool (Spotfire, Tableau, Power BI etc) and SQL scripting (Microsoft, Oracle) will be an added advantage
Familiar with applied machine learning modelling
Partition analysis, Decision tree analysis
Familiar with systematic problem-solving approach
Model based problem solving (MBPS), Kepner Tregoe (KT)
Innovative thinking and leading cross-functional debug teams or working groups are critical as well.
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