Candidate must possess a Bachelors and Masters Degree in Electronics or Computer Engineering or Computer Science or related field of study. Strong verbal communication skills problem solving skills and producing results in a challenging fast paced environment. Good understanding of IP development life cycle tool flow methodology and quality requirements. Good analytical and debugging skills. Working experience in scripting (perl, tcl, python etc). Knowledge on Computer architecture or bus architecture protocols. Basic Knowledge of Verilog, System Verilog, RTL simulation tools and verification is a plus. Knowledge in C programming is a plus