Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.
5 years of experience in micro-architecture and design of IPs and Subsystems in networking domain such as packet processing, bandwidth management, congestion control etc.
Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
Preferred qualifications:
Experience with scripting languages (e.g., Python or Perl).
Experience in SoC designs and integration flows.
Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.