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Intel SoC Logic Design Engineer India, Karnataka, Bengaluru 125629968
Intel Automotive is a Business Group within Corporate Strategy Executive Office responsible for automotive SOC and platform solution development. Future of Automotive is trending towards open, consolidated, Software driven and connected network resulting in requirement of leading Silicon nodes to support software first architecture allowing future feature updates. Automotive brings significant opportunities in SOC architecture and design with challenges on safety, security, quality, reliability, and power. Team is developing new Automotive IVI and Centralized Compute Application SOC's with strong project roadmap. In this position you will be part of a world class SoC DFx team responsible for design, development and validation of DFx solutions for next generation Intel's Automotive SoC's.
Skillset required are the following –
- Experience with creation of micro-arch plans and test environment for RTL design and verification for DFx blocks.
- Experience in development and deployment of verification strategies and methodologies across teams and organizations.
- Proficiency in SystemVerilog for verification, design.
- Development of testplans, test writing and execution for DFx blocks.
- Proficiency in working with structural design teams to ensure timing closure and other quality metrix for DFx units.
- Very good knowledge of SoC validation and integration aspects either using Intel flows or industry standard flows. (ultibuild, cheetah, Defacto etc).
- Expert level knowledge of scripting languages like shell scripting and PERL.
- Experience in TAP/ijtag, MBIST, Scan insertion, spyglass, ATPG tools and GLS, Scan_Controllers, Tessent native TFM, VISA, DTF and DFD features and good exposure to SoC DFx architecture.
- Definition/development and validation of DFx for both Intel and external process technologies and exposure of working with MFG/TD/Component-debug/iVE teams for post-si enablement, debug.
- Strong knowledge of intel internal and external DFx architecture.
- Working knowledge of POST(power on self test), IFT(in field test), FuSa (func safety) methodologies and associated DFT architectures for automotive and industrial usecase.
- Working knowledge of Tessent Native DFT TFM.
Qualifications
- Minimum of 4 years of domain experience out of which 2+ years of hands-on verification, DFT experience using SystemVerilog/verilog
- Strong understanding of engineering design principles
- Good track record of execution in Pre-Si, Post-si Val environments
- Excellent written and verbal communication skills.
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