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Google CPU Power Engineer Silicon 
Taiwan, New Taipei 
119449451

10.06.2024

Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  • Experience with low-power dynamic and leakage, power estimation, as well as data analytics, and profiling.
  • Experience in flow automation (e.g., Python, C, C++).

Preferred qualifications:
  • 3 years of experience in RTL design and low-power design techniques.
  • Experience with the concept of power management, retention, or Dynamic Voltage and Frequency Scaling (DVFS).
  • Experience with vendor tools (e.g., PTPX, Ansys Power Artist, Synopses Prime Power RTL).
  • Experience with CPU bench-marking, performance analysis, and competitive study.
  • Knowledge of CPU micro-architecture.