To implement designs of varying complexity using suitable flows.
To work towards continuous improvement of CPU performance, power and area metrics as an opportunity to improve soft IP, the implementation flow, Physical IP and EDA tools
To contribute to peer reviews and quality inspections
To work with various EDA vendors to improvise the methodologies and develop solutions for advanced technology implementations
Interact with partners to understand their requirements and to support them as and when needed
Required Skills and Experience :
Bachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.
8+ years of proven experience in ASIC system-on-chip implementation flow from RTL to GDS.
Possess a high level of dedicated, initiative and problem-solving skills.
Experience of tape outs of multi-million gate designs on latest technologies
Knowledge of low power and high-performance implementation techniques
Ability to develop and work with timing constraints for build and signoff
Ability to work collaboratively with multiple design centers across multiple time zones
The ability to effectively work alone as well as in a team
Have good interpersonal skills to enable networking both internally and externally to Arm
“Nice To Have” Skills and Experience :
Experience with a wide range of programming, scripting & data presentation languages Eg. Tcl, Shell, Perl, Python.
Experience with low power design techniques (power gating, voltage/frequency scaling).