RTL design using Verilog or SystemVerilog, assertion writing. Design of state machines, data paths, arbitration and clock domain crossing logic. Logic synthesis, timing constraints. Exposure to Design For Test, understanding...
- Direct experience on solving interdisciplinary problems via machine learning (ML). - Publications in top machine learning conferences/journals such as JMLR, ICLR, NeurIPS, ICML, ACL, CVPR. - Knowledge in Algorithms,...
RTL design using Verilog or SystemVerilog, assertion writing. Design of state machines, data paths, arbitration and clock domain crossing logic. Logic synthesis, timing constraints. Exposure to Design For Test, understanding...