דרושים Taiwan, New Taipei

What You'll Be Doing:

• Post-layout model extraction for project review sign-off

• pre-layout model extraction for DOE

• Work closely w/ Package and PCB Design teams to design and ensure link performance meets expectation before tapeout

• Develop novel algorithms & new methodologies to improve SI/PI/EMI modeling efforts

• Work w/ Application Engineering teams to support customers w/ SI/PI questions

• Support signal integrity simulation and analysis for interfaces PCIE, NVLink, display, LPDDR etc.

What We Need To See:

• MS in EE and majoring in SI/PI technology

• Strong understanding of electromagnetics, specifically electromagnetic waves including transmission line theory and via properties, and the SI/PI/EMI applications; S/Y/Z parameters; discrete signal processing knowledge

• Know how to use ANSYSHFSS/Q3D/SIwave/Designer,Synopsis HSPICE, Cadence PowerSI, and Keysight ADS

• Understanding of high-volume manufacturing variations and impact to channel signal integrity is a plus

• Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design , and equalization schemes

• Familiarity with transient simulation in tools and understanding of eye diagram methodology

• Exposure to lab measurements including VNA & TDR, and oscilloscope experience

• Passionate about SI/PI work

Ways To Stand Out From The Crowd:

• SI analysis flow including frequency and time domain simulation

• PDN analysis flow including model generation and time domain simulation

• PSIJ Analyses involving co-simulation of circuits and PDN models

• Experience w/ Matlab, Python, VBS, and C

• RF/microwave engineering; EMI/RFI analysis capability

What you will be doing:

• Work closely with other HW engineering teams such as silicondesign/characterizationteams, IO design/validation teams, system feature owners, operations to determine coverage needs and constraints to resolve appropriate test conditions, diagnostic contents for production line screen.

• Define requirements to SW and board teams to support/improve test infrastructure, debug knobs and data collection features needed to support manufacturing screens effectively.

• Craft creative solutions and workarounds through volume data analysis and lab experimentation to solve challenging yield and test problems seen in production.

• Lead optimization and continuous improvement efforts on the production screen spec definition processes to minimize waste and meet test time, yield, DPPM requirements.

• Support customer facing and quality teams during customer escalations to understand the issue and fix gaps identified in coverage.

• Define procedures to facilitate correlation activities between production testing infrastructure and internal diagnostic programs.

• Create key performance indicators used to evaluate the effectiveness of the new tests.

What we need to see:

• BS or MS degree in EE/CE, or equivalent experience.

• 5+ years of relevant industry experience.

• Strong EE fundamentals, knowledgeable in digital design, signal integrity, statistics, timing analysis, fault analysis, sampling and computer architecture.

• SLT experience. Strong data analysis skills. Prior experience working with volume data is a plus.

• Validated hands-on lab experience with silicon bringup and lab debug.

• Good understanding of firmware/driver structures and their interaction with HW.

• Problem solving, debugging, analysis and logical reasoning skills with examples to prove it.

• Experience with Python, BASH, Linux.

Ways to stand out from the crowd:

• Deep understanding of technology and passionate about what you do.

• Familiarity with statistical methods and tools for data analysis.

• Strong collaborative and communication skills, specifically a shown ability to effectively guide and influence within a dynamic environment.

• Strive to be a standout colleague and be ready to work with global teams from diverse cultural backgrounds in a high energy environment.

What you’ll be doing:

• Study and develop data analytics, and perform in-depth analysis and optimization to ensure the best possible performance on current and next-generation GPU architectures.

• Work directly with key customers to understand the current and future problems they are solving.

• Collaborate closely with the architecture, research, libraries, tools, and system software teams at NVIDIA to influence the design of next-generation architectures, software platforms, and programming models.

What we need to see:

• BS degree from university in an engineering or computer science related discipline (MS or PhD preferred).

• Expert mathematical fundamentals, including linear algebra and numerical methods.

• Strong knowledge of Fortran and/or C/C++.

• Good communication and organization skills, with a logical approach to problem solving, good time management, and task prioritization skills.

• Experience with parallel programming, ideally OpenACC and CUDA C/C++.