דרושים Physical Design Engineer ב-אנבידיה ב-China, Shanghai

You will be part of global Performance Lab team, improving our capacity to expertly and accurately benchmark state-of-the-art datacenter applications and products. We also work to develop infrastructures and solutions that enhance the team’s ability to gather data through automation and designing efficient processes for testing a wide variety of applications and hardware. The data that we collect drives marketing/sales collaterals as well as engineering studies for future products. You will have the opportunity to work with multi-functional teams and in a dynamic environment where multiple projects will be active at once and priorities may shift frequently.

What you’ll be doing:

• Benchmark, profile, and analyze the performance of AI workloads specifically tailored for large-scale LLM training and inference, as well as High-Performance Computing (HPC) on NVIDIA supercomputers and distributed systems.

• Aggregate and produce written reports with the testing data for internal sales, marketing, SW, and HW teams.

• Develop Python scripts to automate the testing of various applications.

• Collaborate with internal teams to debug and improve performance issues.

• Assist with the development of tools and processes that improve our ability to perform automated testing.

• Setup and configure systems with appropriate hardware and software to run benchmarks.

What we need to see:

• Currently pursuing a bachelor's degree (or higher) in Computer Science, Electrical Engineering, or a related field.

• Experienced in programming and debugging with scripting languages such as Python or Unix shell.

• Strong data analysis skills and the ability to summarize findings in a written report.

• Hands-on experience with Linux based systems. Familiarity using a container platform such as Docker or Singularity. Experience with compiling and running software from source code.

• Good English verbal and written skills to improve collaboration with coworkers.

• Fast and self-learning capabilities.

Ways to stand out from the crowd:

• Experience with CI/CD pipelines and modern DevOps practices. Familiar with cloud provisioning and scheduling tools (Kubernetes, SLURM).

• Curiosity about GPUs, TPUs, cloud and performance benchmarking.

• Familiar with ML/DL techniques, algorithms and frameworks like TensorFlow or PyTorch. Experience in AI model inference deployment and training launching.

• Background of system-level problem solving.

What You’ll Be Doing

• Develop comprehensive test plans and implement them using formal verification tools.

• Create assertions, assumptions, and cover properties to validate design behavior.

• Employ abstraction techniques to manage complexity and achieve verification goals.

• Analyze and debug failures in the RTL design.

• Collaborate with architecture, design, and verification teams to communicate coverage and ensure design quality.

What we need to see:

• BS/MS/PhD in CS, CE, EE, or Mathematics (or equivalent experience)with 3+ years relevant experience

• Strong problem-solving skills and the ability to thrive in a collaborative, distributed team environment.

• Proficiency in scripting languages like TCL, Python, or Perl.

Ways to stand out from the crowd:

• Hands-on experience with formal verification tools such as JasperGold or VC Formal.

• Experience with formal verification methodologies, SystemVerilog, and temporal logic.

What you'll be doing:

• Working with customers, partners, and IP vendors to understand SOC/IP solutions best suited for the target use cases and work with them to select and integrate appropriate IP/SOC solutions.

• Work with Architects, Chip Leads, and Customers on SOC/IP design, development, timing closure, power analysis, methodology alignment, and program execution to ensure pre-silicon and post-silicon targets are met.

• Integrating, evolving, and optimizing IP blocks across a range of products and use cases for

  NVIDIA
  SoCs in AI, driving, 6G, cloud, gaming, and other applications.

• Working with teams throughout the company (Architects, RTL, PD, Circuit, SI, Thermal, SW, Platform, Operations, Marketing, etc...) on implementing cross-team solutions to achieve project targets.

• Drive cross-team methodologies for external soft IP and PHY integration, Nvidia IP release to partner, RTL development and microarchitecture.

What we need to see:

• B.S. or M.S. in Computer Engineering or Electrical Engineering (or equivalent experience)

• 9+ years of relevant work experience in RTL development focused on CPU

  , GPU,
  and high-performance architectures.

• Proficiency in industry-standard RTL development and synthesis tools.

• Experience developing high-speed digital blocks.

• Experience debugging complex microarchitectural structures

• Strong interpersonal, communication, and teamwork skills.

• A drive to continuously learn and expand architectural breadth and depth.

• Ability to evaluate microarchitectural options for tradeoffs across design, verification, and PD.

• Experience interconnecting and analyzing complex microarchitectural structures and subsystems.

Ways to stand out from the crowd:

• Cross-cultural work and study experience

• Experience in ARM-based SOC definition and development

• Background in partner and customer engagement for usecase/chip solution.

• Experience in some of domains, SOC clock implementation, power structure insertion, DFT, synthesis, place and route and STA.

What you’ll be doing:

• A role in physical design for NVIDIA GPU and Mobile chips.

• Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification.

• Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.

What we need to see:

• BS in Engineering or Science or equivalent experience.

• Power user of EDA tools from Synopsys(ICC2/FC/PT/STAR-RC),Cadence(EDI/Innovus/Voltus).

• Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes.

• 2+ years of experience in above areas.

Ways to stand out from the crowd:

• MS in Engineering or Science.

• Knowledge in FinFET technology, circuit design, and package design.

• Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre).

• Proficiency in Perl, Python, TCL and Makefile scripts.

NVIDIA SOC System-ASIC team is hiring a verification engineer. In this role, you will work closely with Arch, design and verification engineers to thoroughly verify some top-level related control units (like: Fuse/Floorsweep, Strap, Reset, Sysctrl) and some silicon measurement related units from unit-level to fullchip-level. Those units are important IPs used in both NVIDIA GPU and Tegra products.

What you’ll be doing:

• Micro-architecture definition for System-level modules (Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl, etc...)

• Unit-level and System-level verification for System-level modules.

• Own some NVIDIA internal checks to guarantee the design quality.

What we need to see:

• BS / MS or equivalent experience in electrical / computer engineering and related.

• Above 5 years of ASIC design/verification experience.

• Familiar with verification methodology, tools and flow.

• Understand frontend ASIC design flow including RTL design, synthesis and timing analysis.

• Excellent analytical and problem-solving skills.

• Fluent English (both written and spoken) and excellent communication skills.

• Good team work spirit, easy to cooperate with team members.

Ways to stand out from the crowd:

• Broad knowledge with Video techniques, SOC architecture and Computer architecture is a big plus.

• Strong programming skills in C/C++, SystemVerilog, Perl and Python is appreciated as a plus.

What you’ll be doing:

• Be responsible for running test cases to validate NVIDIA GPU Communications Libraries (NCCL, NVSHMEM, UCX, GDRCopy, GPUDirect RDMA etc).

• Be responsible to automate test cases and maintain the automation scripts.

• Collaborate with Developer, PM, marketing, and engineering teams on crafting test plan and implementing validation.

• You will assist in the architecture, crafting and implementing of SWQA test frameworks.

• Be responsible for code coverage improvement and code complexity optimization.

What we need to see:

• BS or higher degree in CS/EE/CE or equivalent experience

• 5+ years of relevant experience

• Seasoned software QA or software testing background; test infrastructure and strong analysis skills

• Be proficient in scripting language (Python, Perl, bash)

• Solid experience with AI development tools for test development and automation

• Knowledge of basic networking concepts

• UNIX/Linux experience is required

• Experiences in C/C++ is required

• Ability to work independently and leadership skillsas well as experience in using quality mindset to drive improvements

• Proficient oral and written English

Ways to stand out from the crowd:

• Experience with CUDA programming and NVIDIA GPUs

• Knowledge of high-performance networks like InfiniBand, RoCE,etc

• Experience with CSPs(AWS, Google Cloud, Oracle Cloud Infrastructure, Microsoft Azure), andHPC cluster,slurm, ansible, etc

• Prior experience with virtualization technologies (KVM, HyperV, VMWARE, OpenStack, Docker, Kubernetes)

• Experience with Deep Learning Frameworks such as PyTorch, TensorFlow, etc

What you’ll be doing:

• Work with architects and performance architects to develop an energy-efficient GPU.

• Develop methodologies and workflows to select and run a wide variety of workloads to train models using ML and/or statistical techniques.

• Develop methodologies to improve the accuracy of energy models under various constraints, such as, process, timing, floorplan and layout.

• Correlate the predicted energy from models created at different stages of the design cycle, with the goal of bridging early estimates to silicon.

• Develop tools to debug energy inefficiencies observed in various workloads run on silicon, RTL and architectural simulators. Work with architects to fix the identified energy inefficiencies.

• Work with performance, verification and emulation methodology and infrastructure development teams to integrate energy models into their platforms.

• Prototype new architectural features, create an energy model, and analyze the system impact.

What we need to see:

• MS degree with 1 year experience in related fields or equivalent experience

• Strong coding skills, preferably in Python, C++.

• Background in machine learning, AI, and/or statistical modeling.

• Interest in computer architecture and energy-efficient GPU designs.

• Familiarity with Verilog and ASIC design principles is a plus.

• Ability to formulate and analyze algorithms, and comment on their runtime and memory complexities.

• Desire to bring quantitative decision-making and analytics to improve the energy efficiency of our products.

• Good verbal/written English and interpersonal skills.