דרושים Marvell - משרות Marvell

What You Can Expect

In this role you will be responsible for:

• Active circuit design and verification of High-performance broadband analog circuits for optical front-end receivers.
• Working with various other analog circuits including linear regulators, AGC loops, current/voltage sensors, bandgaps etc. Working with various technologies including SiGe BiCMOS and CMOS.
• Working in a team to deliver full-chip TIA solutions.
• Developing transmission line structures and other millimeter wave structures to enable higher performance than would normally be achievable.
  

What We're Looking For

• Must be currently enrolled at an accredited college or university pursuing a Ph. D in relevant Electrical / Computer Engineering related program OR combination of MS coursework and relevant experience
• Proven experience in analog IC design including chip tape-out and lab measurement is a plus
• Solid experience using EDA CAD tools and performing Analog Custom Layout
• Deep understanding of fundamentals, including detailed transistor level design, device physics, control/Feedback loop stability analysis
• Experience in using different technologies (SiGe BiCMOS is a plus)
• A team-player, strong communication, presentation, and documentation skills
• Experience in at least one of the following areas is a plus: Transimpedance amplifier stages, variable Gain Broadband amplifiers, matched Transmission line drivers, CTLE design, AGC loop design, high precision analog circuits (Including linear regulators, current sensors, bandgaps, and DAC/ADC)

Expected Base Pay Range (USD)

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

What You Can Expect

• Responsible for MBIST/BSCAN/SCAN insertion, DFT simulation, DFT SDC
• Work closely with various multi-functional teams on resolving complex issues to ensure successful Tape-out

What We're Looking For

• Thorough knowledge of DFT insertion & verification flow and methodology
• At least 3+ years’ experience in DFT field. Expertise in DFT tools and flow
• Hands on experience in DFT SDC constraints generation and management for block level and full chip level
• Hands on experience in debugging DFT simulation & ATE failure
• Knowledge of SYN/STA/PnR is a plus
• Proficient in scripting languages (TCL and Perl)