דרושים Graduate Intern Hw Logic Design ב-אינטל ב-ארהב

The job Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block.

As ayour responsibilities will include but are not limited to:

• You will be responsible for designing and/or integrating IP for a discrete graphics SoC. You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation of discrete graphics SoC products, including:

• Creating a design to produce key assets that help improve product KPIs for discrete graphics products.

• Working with SoC Architecture and platform architecture teams to establish silicon requirements.

• Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule.

• Creating micro architectural specification document for the design.

• Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs.

• Driving vendor's methodology to meet world class silicon design standards.

• Architecting area and power efficient low latency designs with scalabilities and flexibilities.

• Power and Area efficient RTL logic design and DV support.

• Running tools to ensure lint-free and CDC/RDC clean design, VCLP.

• Synthesis and timing constraints.

The ideal candidate will exhibit the following behavioral traits:

• Ability to drive and improve digital design methodology to achieve high quality first silicon

• Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule

• Strong verbal and written communication skills

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimumqualifications:

• Bachelors degree in Electrical, Computer Engineering with 4+ Years relevant experience in the semiconductor industry.

• OR Masters degree in Elecrtical, Computer Engineering with 3+ years relevant experience in the semiconductor industry

• 4+ years of experience in/with:

  • Verilog and system verilog, synthesizeable RTL

  • Modern design techniques and energy-efficient/low power logic design and power analysis

  • Computer Architecture

Preferred qualifications:

• Experience with FPGA emulation, silicon bring-up, characterization and debug

• Experience in multiple tape-outs reaching production with first pass silicon

Benefits:

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Microcode Development

• Design and implement microcode for complex instruction sets (x86 or proprietary architectures).
• Analyzing existing developed code, understanding and gathering new requirements, developing new algorithms or changes required, documenting for review and communication, creating and negotiating a development plan, writing the code, and debugging that code for functionality and performance requirements.
• Interacting and communicating with Architecture, Logic design, and Validation teams to achieve their coding goals.
• Supporting this code through tape-in and future steppings, either through patching or code rewrites.
• Being a member of the Microcode team, candidate will also be reviewing others' code and helping to improve group productivity and accuracy.

Architecture & Design

• Defining and developing innovative Architecture and Microarchitecture for Intel's next generation E-core Microprocessor.
• Collaborate with CPU architects to understand instruction set requirements and performance targets.
• Analyze instruction execution flows and optimize microcode for performance, power, and area efficiency.
• Design microcode control structures and sequencing logic.
• Participate in microarchitecture definition and specification reviews.

Verification & Testing

• Develop comprehensive test plans and verification strategies for microcode functionality.
• Create and execute microcode test cases using simulation environments.
• Debug microcode issues using advanced debugging tools and methodologies.
• Collaborate with validation teams to ensure proper microcode coverage in silicon testing.

Optimization & Performance

• Profile and analyze microcode performance using performance monitoring tools.
• Identify and resolve performance bottlenecks in instruction execution paths.
• Optimize microcode for specific workloads and benchmark requirements.
• Implement power management features within microcode constraints.

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, and internships experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying topcandidates.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering or in a STEM related field of study.
• 5+ years of experience in CPU microcode development or processor design.
• 2+ years' experience with firmware development in C or C++.
• 1+ years' experience or education in Computer Architecture and/or Micro Architecture techniques.
• 1+ years' experience with logic design using Verilog and debug using industry standard tools.

Preferred Qualifications

• Post Graduate degree in Computer Science, Electrical Engineering, Computer Engineering or in a STEM related field of study.
• Experience simulator development using C++.
• Experience in logic design using Verilog and debug using industry standard tools.
• Experience with CPUarchitecture/assembly(i.e. Intel x86, AMD, ARM Cortex, etc.).

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

• Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.

• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.

• Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.

• Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.

• Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelors degree in Computer Engineering, Electrical Engineering or STEM related field with 3+ years of relevant work experience

• -OR- Masters degree in Computer Engineering, Electrical Engineering or STEM related field with 2+ years of relevant work experience

• -OR- PhD degree in Computer Engineering, Electrical Engineering or STEM related field

Relevant experience should include the following:

• Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure

• PV convergence (including static timing and power analysis)

• Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.

• Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)

• Demonstrated success in one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP

Preferred Qualifications:

• 2+ years of industry experience/exposure with CPU Micro-Architecture

• Experience with Physical design best known practices concerning floor-planning, routing techniques, clock distribution

• Experience with of Static Timing Analysis, Noise analysis, and reliability verification techniques

• Experience with of RTL to GDS methodologies and formal equivalence

• Experience with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

You Are

Your responsibilities will include but not be limited to:

• Adding support for new features/IPs into existing emulation models

• Learning architecture and microarchitecture by debugging failures to the root cause

• Developing high level (for example, C++/Python) modeling for RTL components

• Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design

• Building multiple emulation targets for an SoC

• Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models

• System level validation tasks such as using evaluation boards and FPGAs

• SOC level feature enabling/debug

The ideal candidate should exhibit the following behavioral traits:

• Problem-solving skills

• Ability to multitask

• Strong written and verbal communication skills

• Ability to work in a dynamic and team-oriented environment

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• The candidate must have a Bachelor’s Degree in Computer Science, Computer Engineering or Electrical Engineering with 3+ years of relevant experience -OR- Master’s Degree in Computer Science, Computer Engineering or Electrical Engineering 2+ years of relevant experience

Preferred Qualifications

• Experience with reading and interpreting technical specs and Register Transfer Level (RTL) code

• Experience with validation or testing experience, especially in a silicon design team

• Experience with UNIX or Linux

• Experience with IA-32 assembly and/or Verilog programming experience

• Experience writing BFMs

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

will be responsible for, but not limited to:

• Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to fix violations for current and future product architecture.
• Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
• Optimizes design to improve product level parameters such as power, frequency, and area.
• Participates in the development and improvement of physical design methodologies and flow automation.

The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / orschoolwork/classes/research.The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• Experience in leading small team of engineers.
• 7+ years of experience with complex ASIC/SOC Implementation.
• Experience in system and processor architecture.
• Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller.
• Experience with System Verilog/SOC development environment.
• Experience in scripting languages (i.e. PERL, TCL, or Python).
• Experience with Hardware validation techniques (i.e. formal Verification, Test and Function Verification).

Preferred Qualifications:

• Post graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• Experience with Industry standard protocols (i.e. PCIE, USB, DRR, etc).
• Experience with interaction of computer hardware with software.
• Experience with Low power/UPFimplementation/verificationtechniques.
• Experience with Formal verification techniques.

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

will be responsible for, but not limited to:

• Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to fix violations for current and future product architecture.
• Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
• Optimizes design to improve product level parameters such as power, frequency, and area.
• Participates in the development and improvement of physical design methodologies and flow automation.

The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / orschoolwork/classes/research.The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• 5+ years of experience with complex ASIC/SOC Implementation.
• Experience in system and processor architecture.
• Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller.
• Experience with System Verilog/SOC development environment.
• Experience in scripting languages (i.e. PERL, TCL, or Python).
• Experience with Hardware validation techniques (i.e. formal Verification, Test and Function Verification).

Preferred Qualifications:

• Post graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• Experience with Industry standard protocols (i.e. PCIE, USB, DRR, etc).
• Experience with interaction of computer hardware with software.
• Experience with Low power/UPFimplementation/verificationtechniques.
• Experience with Formal verification techniques.

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

will be responsible for, but not limited to:

• Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to fix violations for current and future product architecture.
• Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
• Optimizes design to improve product level parameters such as power, frequency, and area.
• Participates in the development and improvement of physical design methodologies and flow automation.

The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / orschoolwork/classes/research.The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• Experience in leading small team of engineers.
• 7+ years of experience with complex ASIC/SOC Implementation.
• Experience in system and processor architecture.
• Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller.
• Experience with System Verilog/SOC development environment.
• Experience in scripting languages (i.e. PERL, TCL, or Python).
• Experience with Hardware validation techniques (i.e. formal Verification, Test and Function Verification).

Preferred Qualifications:

• Post graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• Experience with Industry standard protocols (i.e. PCIE, USB, DRR, etc)
• Experience with interaction of computer hardware with software
• Experience with Low power/UPFimplementation/verificationtechniques.
• Experience with Formal verification techniques.

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: