דרושים Fpga Silicon Dft Manager ב-אינטל ב-מלזיה

• Translates product requirements into package architecture specification, drives end-to-end package solutions for physical, electrical, and cost requirements.
• Leads technology tradeoff decisions ensuring silicon packages conform to electrical, mechanical, thermal, and reliability standards, specifications, and landing zones.
• Collaborates with silicon, hardware, and package leads to ensure high quality package output and aids in removing roadblocks.
• Oversees end-to-end package development process, including design, processes, and procedures and continuously improves packaging quality standards and targets.
• Applies expertise in package design troubleshooting, resolves new and existing packaging problems involving designs, materials, and processes and provides innovative and cost-effective solutions.
• Collaborates with manufacturing team to ensure the packaging design and tape-out seamlessly transition to production.

• Bachelor Degree in relevant engineering/science domain with minimum 10 years of experience in the package design and/or architecture.
• Prior leadership role in package technology readiness development, design tape-out and/or innovation.

• Translates product requirements into package architecture specification, drives end-to-end package solutions for physical, electrical, and cost requirements.
• Leads technology tradeoff decisions ensuring silicon packages conform to electrical, mechanical, thermal, and reliability standards, specifications, and landing zones.
• Collaborates with silicon, hardware, and package leads to ensure high quality package output and aids in removing roadblocks.
• Oversees end-to-end package development process, including design, processes, and procedures and continuously improves packaging quality standards and targets.
• Applies expertise in package design troubleshooting, resolves new and existing packaging problems involving designs, materials, and processes and provides innovative and cost-effective solutions.
• Collaborates with manufacturing team to ensure the packaging design and tape-out seamlessly transition to production.

• Bachelor Degree in relevant engineering/science domain with minimum 10 years of experience in the package design and/or architecture.
• Prior leadership role in package technology readiness development, design tape-out and/or innovation.

• Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including BSCAN).
• Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, BSCAN, proc monitors, in system test/BIST).
• Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
• Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block. Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
• Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
• 5+ years of experience in DFT, SOC design, or related semiconductor design areas. Strong knowledge of DFT techniques, including BIST, boundary scan, JTAG, and fault simulation.
• Experience with EDA tools for DFT (e.g., Synopsys DFT Compiler, Mentor Tessent, Cadence Modus, ATPG).Proficiency in hardware description languages such as VHDL, Verilog, or System Verilog.
• Expertise in automated test generation and analysis tools. Strong problem-solving skills with the ability to troubleshoot complex testability issues. Experience with RTL design and verification processes.
• Excellent communication and teamwork skills to collaborate with multi-disciplinary teams. Ability to analyze, review, and optimize existing DFT strategies for design and test coverage. Familiarity with semiconductor manufacturing processes and test flows.

Preferred Qualifications :

• Experience with advanced test techniques such as DFT for low-power designs. Familiarity with industry standards such as IEEE 1687 (IJTAG), 1149.1 (JTAG), IEEE 1500 (Core Test), and others.
• Knowledge of Python or other scripting languages for automation.
• Experience with failure analysis, yield improvement and test cost optimization methodologies.
• Experience with SOC (System on Chip) or complex multi-chip designs requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

• Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools.
• Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware.
• Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability.
• Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, post silicon validation, and software development.
• Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency.
• Develops and utilizes automation aids, flows, and scripts in support of emulation utilization.
• Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model).
• Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues.

• Bachelor’s or master’s degree in electronic and electrical engineering, Computer Engineering, or Mechatronics Engineering,
• Strong problem-solving and analytical skills.

Preferred Qualifications:

• Experience in RTL, FPGA, emulation, and SoC systems is a plus.
• Coursework or academic projects involving system-level validation, digital design, or emulation would be advantageous.
• Familiarity with FPGA tools (e.g., Xilinx Vivado, Intel Quartus) is a plus.
• Exposure to emulation platforms (e.g., Cadence Palladium, Synopsys ZeBu, Mentor Veloce) is desirable.

In this position, you will be involving in the training, design and development of next generation SOC/CPU for wide range of Intel products. Your responsibilities will include some of the following but not limited to:

• Assist design unit owner in Register Transfer Level RTL model functional validation.

• Use CAD tool extensively to simulate logic behavior and circuit performance and direction of physical design for next generation, deep sub-micron embedded circuit solutions.

• Verify the circuit behavior against the original simulation model and first silicon.

• Define VLSI Structural Design methodology and developing design flows.

• Implement structural physical designs, such as synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration.

• Verify structural physical designs, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power.

• Develop Analog IP on next generation deep submicron process for the Intel's SOC, perform tasks related to Very-large-scale integration VLSI complementarymetal-oxide-semiconductorCMOS IC design, Solid state physics and physical layout. Such tasks may include Circuit design of high-speed clocking related circuits [phase-locked loop PLL, delay-locked loop DLL, bandgap] or high voltage input/output IO [double data rate DDR/LPDDR, General-purpose input/output GPIO, OPIO].

• Responsible for Integration of Third-party IPs -- Synthesis, functional and/or timing convergence, and pre- and post-si debug of IPs developed by various external vendors as well as within the company.

• Handling of signals crossing power planes and clock domains, industry standard protocols including hardware and software details dealing with Memory LPDDR, storage eMMC, SATA, UFS, peripherals PCIe, USB, and MIPI interfaces in SOC devices.

• System integration dealing with Si/ Platform/ FW/ MW/ drivers/ OS/ Apps on Android Windows-based tablets and phones.

You must possess a Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering. Additional qualifications include:

• Familiarity with Very Large-Scale Integration VLSI Complementary Metal-Oxide Semiconductor CMOS logic circuit design

• Well versed in UNIX, C programming and relevant Computer Aided Design CAD tools.

Responsibilities:

• Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools.
• Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware.
• Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability.
• Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, post silicon validation, and software development.
• Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency.
• Develops and utilizes automation aids, flows, and scripts in support of emulation utilization.
• Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model).
• Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues.

• Bachelor’s or master’s degree in electronic and electrical engineering, Computer Engineering, or Mechatronics Engineering,
• Strong problem-solving and analytical skills.

Preferred Qualifications:

• Experience in RTL, FPGA, emulation, and SoC systems is a plus.
• Coursework or academic projects involving system-level validation, digital design, or emulation would be advantageous.
• Familiarity with FPGA tools (e.g., Xilinx Vivado, Intel Quartus) is a plus.
• Exposure to emulation platforms (e.g., Cadence Palladium, Synopsys ZeBu, Mentor Veloce) is desirable.

We created the Intel Atom Processor (E-Core), a disruptive technology that enables a broad range of devices including entry PC's, smartphones, modems, 2 in 1 laptops, micro-servers, and other Internet-of-Things IoT devices. You will be part of a team, participating in the design of a future generation high performance Intel E-core microprocessor. You will work as a key member of a team participating in the design of E-core CPUs.

The Responsibilities for this position will include but not be limited to:

• Manage a team of design engineers responsible for RTL to GDS activities.
• Plan, allocate resources, assign tasks and direct activities of the team to meet aggressive schedules and achieve milestone criteria.
• Identify and analyse progress gating issues and implement plans, tasks, and provide quick solutions.
• Propose creative, innovative methodology and process initiatives to consistently improve efficiency and quality of integration deliverables.
• Provide coaching, guidance and feedback to direct reports on career development, performance, and productivity issues.
• Build a strong and technically vital organization. Cultivate and reinforce appropriate group values, norms and behaviors.

The successful candidate must possess a minimum of a BS or MS in Electrical Engineering or Computer Engineering with at least 7 years of hands on experience in this area and at least 3 years of experience in leading a team either as technical lead or as manager.
Additional qualifications include:Hands-on experience in the following areas:

• Block floor planning, RTL to gate level netlist generation through synthesis, DFT insertion, placement, clock tree synthesis and route flows, power and static timing analysis and closure, validation of physical design including timing, electrical rules, DRC/LVS, noise, electromigration checks, formal equivalence verification.
• Successfully led one or more design tape-outs of complex, high performance, low-power CPUs.
• Able to provide technical leadership to a team of engineers involved in RTL to GDS APR build and verification flows.
• Able to provide technical guidance and support to team members throughout the project design cycle.
• Excellent verbal communication, technical presentation and leadership skills. Self-motivated and well organized.
• Candidate should be familiar with Synopsys or Cadence build tools.