דרושים Asic Technical Design Lead Engineer ב-Cisco ב-Armenia, Yerevan

You will be in the Silicon One development organization as a senior DFT verification lead in Armenia. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification.

• Taking part in all aspects of digital design, from micro-architecture to RTL design and qualification.
• Sub-system/SoC integration and verification.
• Review/enhancement of RTL codes.
• Improve flows and methodologies to streamline IP/SoC development and integration.
• Work closely with the verification team for complex debugs to resolve verification failures.
• Close interaction with physical design team to reach better physical design QoR.

• 7+ years of industry experience in ASIC digital design.
• Proficient in Verilog/System Verilog coding.
• Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).
• Experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories.
• Ability to write scripts using Python, Tcl, Make.
• Good communications skills, self-motivated and well-organized.

• Familiarity with power optimization techniques , power intent (UPF), power estimation.
• Familiarity with DFT/MBIST is a plus

You will be in the Silicon One development organization as a senior DFT verification lead in Armenia. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification.

• Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation and post silicon validation flows.
• Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.
• Work with the team on DFT challenge identification, cross-functional solution brainstorming and implementation plan development, and lead junior engineers to deliver expected implementations on schedule.
• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

• Bachelor's or Master’s Degree in Electrical or Computer Engineering required with at least 10 years of experience.
• Prior experience in test planning based on complex design specification.
• Prior experience in testbench development using System Verilog.
• Debugging experience using DVE/Verdi.
• Scripting skills: Tcl, Python/Perl.

• UVM and advanced System Verilog knowledge.
• Knowledge about JTAG protocol, scan architecture, MBIST and boundary scan.

• Perform full-chip EM/IR analysis, debug issues, provide solutions, and ensure signoff clean results.
• Conduct voltage-aware STA at both full-chip and block levels, review and resolve issues to achieve timing closure.
• Implement full-chip and block-based ECOs for EM/IR violations, refining strategies to ensure seamless execution.
• Generate and implement manual ECOs for EM/IR challenges.
• Collaborate closely with block-level physical design teams to understand implementation challenges and ensure alignment.
• Perform full-chip and block-level ESD Resistance/CD analysis, debug issues, and ensure clean signoff results.

• Strong knowledge and expertise in EM/IR analysis, including debugging and developing effective solutions.
• 3+ years of experience working with deep submicron CMOS technologies.
• Solid understanding of the CMOS Digital Design Flow and its applications.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.

• Comprehensive expertise of the full physical design cycle from RTL to GDSII.
• First-hand experience with EM/IR and ESD analysis.
• Proficiency in scripting languages such as Tcl, Python, or Shell to improve efficiency.
• Excellent verbal and written communication skills in English.

• You will be responsible for macro level RTL to gds implementation and signoff.
• Work with Front-End teams to understand the design architecture to ensure optimal physical implementation.
• Execute critical physical design tasks, including gate-level netlist synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing.
• Optimize designs to achieve industry-leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification.
• Conduct Static Timing Analysis (STA), physical verification,formal verificationand signoff closure to ensure high-quality results.
• Analyze and resolve Electromigration (EM) and IR-drop (IR) issues, meeting stringent signoff requirements for reliability and performance.

• Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
• 6+ year minimum of hands-on experience in ASIC design and verification
• Proven expertise in ASIC physical design and verification with a strong track record of delivering complex projects.
• Advanced knowledge of block-level synthesis, place-and-route (PnR), and timing closure.
• First-hand experience with industry-standard PnR and signoff tools such as Synopsys and Cadence.

• Comprehensive understanding of all aspects of physical design construction, integration, and methodologies.
• Proficiency in Physical Design Verification, including techniques like LVS and DRC.
• Experience with physical design EDA tools and workflows.
• Advanced expertise in Static Timing Analysis (STA), timing closure, and design constraints.
• Proficiency in scripting languages like Tcl, Python, or Perl, with a focus on automation and efficiency improvements.