דרושים Senior Sap Rar Specialist ב-Arm ב-India, Bengaluru

Job Overview:

Responsibilities:

Required Skills and Experience:

We Prefer graduate or postgraduate from a university or Engineering School, in Electronic Engineering or equivalent Engineering Degree.

· You have 4-8 years of experience in SRAM/memory designs, margin analysis, characterization and verification

· You have some understanding of computer architecture and concepts.

· We expect you to have basic understanding of CMOS Transistors, their behaviors.

· We expect some basic understanding of high speed/low power CMOS circuit design, clocking scheme, static and complex logic circuits.

· Understanding of Power versus Performance versus Area trade-offs in typical CMOS design.

· You have an engineering demeanor and Passion for Circuit design.

· Expected to have good interpersonal skills.

“Nice To Have” Skills and Experience:

· You know basic scripting languages, e.g. Perl/TCL/Python.

· Some Experience of working on Cadence or Synopsys flows.

· Experience with Circuit Simulation and Optimization of standard cells.

· Silicon debug/validation

In Return:

• Define, implement, and maintain methodologies for CDC, RDC, Lint, and CLP analysis.
• Ensure RTL quality through static analysis, debugging, and architectural alignment.
• Collaborate with design teams to interpret specifications and resolve RTL/System Verilog issues.
• Support and maintain flows for analyzing infrastructure IPs and NoC architectures.
• Automate static checks and integrate them into development flows using Python scripting.
• Handle and collaborate using version control systems like Git.

• Expertise in static analysis tools for CDC, RDC, Lint, and CLP.
• Strong experience in delivering clean, high-quality RTL code.
• Ability to interpret and implement architectural and functional specifications.
• Familiarity with infrastructure IPs and Network-on-Chip (NoC) designs.
• Solid understanding of RTL design and debugging with System Verilog.
• Proficiency in Git for version control.
• Scripting experience in Python for tool automation and flow improvement.

• Exposure to front-end integration tools and design methodologies.
• Strong interest and skill in flow development and automation.
• Experience with IP management using IPXACT.
• Understanding of behavioral and synthesized model correlation.

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence
• Deliver on your promises

Job Overview:

It would also be desirable if you have experience with media, graphics or imaging flows and driver/middleware stack development.

Responsibilities:

• Design and implement software components that meet functional safety requirements (e.g., ISO 26262, IEC 61508).
• Work to bring function safety to existing code.
• Develop and maintain documentation to support safety certification and compliance audits.
• Collaborate with safety engineers, hardware teams, and software architects to define software safety requirements and architectures.
• Support software integration, verification, and validation processes in safety-critical systems.
• Contribute to process improvements and tooling for safety-focused software development workflows

Required Skills and Experience:

• Strong proficiency in C development, particularly in embedded or system-level programming.
• Well-versed in functional safety principles, including hazard analysis, safety goals, and ASIL decomposition.
• Motivation and ability to work on frontend tasks using JavaScript.
• Hands-on experience with safety standards such as ISO 26262 or IEC 61508.

“Nice To Have” Skills and Experience :

• Experience with safety analysis tools and methods (e.g., FMEA, FMEDA, fault injection).
• Knowledge of MISRA C/C++ or other safety-related coding standards.
• Background in developing software for automotive, aerospace, or industrial control systems.
• Familiarity with safety certification processes and documentation requirements.
• Knowledge of media, imaging or rendering pipelines.

In Return:

As part of the methodology team, you will lead the development, improvement, and deployment of low power structural check methodologies across multiple SoC and IP projects. This role involves designing automated flows for UPF/CPF consistency, power domain integrity, and structural rule validation at both RTL and netlist levels. You will collaborate closely with design, verification, and EDA partners to ensure robust, scalable, and high-coverage power-aware design signoff strategies across technology nodes and product segments.

• Develop and maintain low-power structural check methodologies (UPF/CPF validation, isolation, level shifters, retention, domain crossings).
• Build automated flows using tools like Synopsys VC LP, SpyGlass-LP, and Conformal LP.
• Ensure power intent consistency and early issue detection through collaboration with design and verification teams.
• Integrate structural checks into signoff regressions with high coverage and low false positives.
• Work with vendors and internal teams to enhance tools, debug issues, and improve efficiency.
• Drive global adoption through documentation, training, and support.
• Assist in audits, quality reviews, and milestone checks.

• 5+ years of Strong background in low-power structural methodologies and UPF/CPF-based flows.
• Deep understanding of power intent specs, domain partitioning, isolation, and retention.
• Hands-on experience with tools like VC LP, SpyGlass-LP, or Cadence CLP.
• Skilled in scripting (Python, Perl, TCL) for flow automation.
• Experience with large SoC/IP designs across advanced nodes.
• Confirmed ability to debug structural issues and drive closure.
• Strong communication and documentation skills.

• Experience with formal verification or functional simulation for power-aware designs.
• Knowledge of complex power analysis and correlation with structural checks.
• Exposure to hierarchical low-power signoff strategies in multi-voltage or multi-power domain SoCs.
• Familiarity with power-aware DFT, scan strategies, and low-power aware synthesis flows.
• Participation in industry working groups (e.g., Accellera UPF), technical conferences, or publications.
• Involvement in tool benchmarking, vendor collaborations, and internal tool qualification projects.

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence
• Deliver on your promises

The purpose of this role is to ensure that various system implementations based on the same architectural specifications, can run standard software from different vendors efficiently and with minimal effort. This will reduce overall market deployment time and enable broad adoption of these system implementations.

Mandatory Skills

- Programming using C/C++/Assembly with experience in software engineering methodologies.

- Software development skills, ideally in the area of firmware / low level operating systems

- Familiar with verification process such as Test Plan development, Test case development

Nice To Have

Familiarity of Unix / Linux working environment, Experience in Linux kernel and UEFI,

- Implementation of bespoke test harness' for O/S and bare metal validation

- Ability to understand and drive complex technical specifications

- Familiarity with EDA tools and Hardware Design Verification/ Emulation based verification

You will be responsible for the development of Arm custom standard cells in the latest, sub-3nm process technology nodes. You will work as part of a team that co-optimizes the circuit design with physical design engineers to improve the PPA of Arm cores that will be integrated into best-in-class SoCs.

You will work in close collaboration with the mask design team to provide optimally tuned layout, characterize and model all standard library views, and validate them through QA flows that use a variety of EDA tools.

• 3+ years of relevant circuit design experience.
• Significant experience in the identification, design and verification of cells specifically targeted to improve core and SoC level PPA
• In-depth understanding of MOSFET electrical characteristics, transistor level device physics, PPA tradeoffs, layout and variability especially at 3nm and below technology nodes
• Expertise in transistor level design of static circuits including state retaining elements such as latches and flops
• Hands-on development of standard cell EDA view characterization, modeling and QA
• Experience with standard cell characterization tools and Spice circuit simulators
• Proficient in scripting languages such as Perl or Python
• Ability and willingness to proactively support the development of others
• Be willing to iteratively improve designs and repeatedly attempt to develop solutions to difficult problems
• Demonstrate a positive attitude and respect for all members of the team
• Be motivated to continuously develop skills and accept various responsibilities as a part of contributing to Arm’s success
• Ability to analyze data and present conclusions effectively

• Ability to lead a team of engineers through project management, delegation, and communication of risks and issues to engineering management
• Exposure to physical design implementation flow and signoff

In this role, you will be part of the Design Space Exploration (DSE) team in the Central Technology Group that analyses system-level power and performance of future technologies, using performance models. DSE team work closely with IP teams, system architects, and product managers to capture technology trends and conduct exploratory studies. This requires a mix of technical, analytical, and communication skills.

Part of your work will be the design and development of the performance models that are used for DSE studies. This will allow you to work on topics like power/thermal modelling, thermal control, job scheduling, caching, and modelling of processing elements, interconnects, and memories. You will use DSE performance models to explore PPA of multiple system architecture candidates for key use cases (e.g., gaming, AI camera, video streaming) to identify the most promising future system architectures. The ideal candidate will also play a key role in identifying new technologies (e.g., new memory types, heterogeneous integration). You will contribute to an exciting, engineering-focused environment in a field that is at the forefront of new technology in the industry.

• Application bring-up / porting to Arm silicon and modelling platforms
• Analyzing software stacks both statically (code structure) and dynamically (runtime performance profiling) to characterize the workloads/algorithms and determine a baseline performance from which to start optimization
• Projecting and measuring gains at the application level
• Evaluating workload sensitivity to micro-architecture features and considering relevant trade-offs, especially related to performance
• Providing suggestions about improvements to the (micro-)architecture & application software
• Developing tools to automate workflow

You will have knowledge and experience in several of these areas:

• Strong C/C++ programming and debugging skills.
• Programming in scripting languages such as Python, Perl, Bash

• Experience with modelling
• Power/thermal modelling
• Digital hardware design (e.g., RTL design, synthesis, physical design)
• Understanding of the basics of CPU microarchitecture, caching, and networking