Senior Staff Research Scientist jobs at Intel in Israel

You will be exposed to High-Speed I/O protocols such as PCIe, DDR5, and PAM4 Ethernet, which are a part of our Ethernet Infrastructure Processing Unit (Intel IPU) and Foundation NIC (FNIC) Ethernet product lines.

In this position:

• You will lead a team of developers and also work hands-on to design and develop digital and analog circuit boards for HW-Engineering products.
• Develop board design from schematic through Silicon power-on debug and may interface with other board design and test module development teams to drive innovation initiatives.
• Identifying new hardware solutions, providing technical leadership to working groups/task forces to resolve hardware, schematics, layout, DFx issues through debugging and reviews, and part/component selection management.
• learning the specification of each interface and the required design limitations that should be verified.
• requires high-frequency signal and power integrity and a good understanding of RF circuits and electromagnetic wave propagation.

• B.Sc./M.Sc. Electrical Engineer with over 10 years of relevant experience in hardware/board design.
• 4+ years as a team lead, including planning and design-flows buildup.
• Experience with PCB technology and layout (Analog and Digital) including stack-up, placement, routing, and SI/PI.
• Lab work experience in high accuracy signals measurement.
• Excellent debugging skills, ability to analyze problems, diagnose the root cause and apply corrective action.
• Familiar with layout technics.
• FPGA and Verilog coding skills.
• Test measurement instrument hands-on operation.
• Programming knowledge and experience.
• Strong verbal and written communication skills in English.
• Comprehensive understanding of system architecture.

About the group: The Infrastructure Processing Unit (IPU), also known as Smart-NIC, is a PCIe-powered network interface card that significantly enhances traditional NIC capabilities by offloading tasks such as packet processing, traffic shaping, virtual switching, and more from the HOST CPU (Xeon). IPUs are the future of cloud processing and storage and are already being deployed in the data centers of the largest and most well-known cloud service providers.About the role: As Senior Embedded Linux driver engineer in our group, you will be part of driver team that deals with variety of challenges like Linux driver architecture, design, implementation, support and debug in system validation platforms (like simulator, emulation, FPGA and Silicon) for Smart NIC Ethernet based products, working in a fast-paced and innovative team environment.Your responsibilities will include:

• Defining and developing innovative drivers for system validation platforms of the Intel's next-generation Smart NIC Ethernet based products.
• Analyzing existing developed driver code, understanding and gathering new requirements, developing new features or changes required, writing the code, and debugging on pre-silicon as well as silicon platforms.
• Integration support of system validation board bring-up on pre-silicon as well as silicon platforms.

Minimum Qualifications:

• B.Sc. in Electrical Engineering / Computer Engineering or Computer Science.
• Relevant 8+ years of hands-on experience in C/C++ development and troubleshooting on embedded platforms.
• Linux experience: Linux Kernel\ Device Driver development on Linux
• Experience with board bring-up and systems debugging
• In-depth understanding of source controlling, in particular with git
• Good familiarity with CI\CD tools
• Effective communication skills, both written and verbal with a keen sense of customer service

The following will be considered as an advantage:

• Hardware debugging experience.
• Knowledge of system architecture
• Experience with Agile (SCRUM) practices
• Experience with Python and/or Bash
• Experience with ARM and Xtensa processors and micro-controllers
• Familiarity with networking concepts, PCIe, ARM-based environment

Responsibilities:

• Development and implementation of comprehensive verification plans and strategies for complex hardware designs, ensuring alignment with industry best practices.
• Oversee the maintenance of verification environments using advanced industry-standard tools and methodologies, mentoring junior engineers in the process.
• Review test cases to verify design functionality and compliance with specifications.
• Collaborate closely with design, architecture, and firmware engineers to deeply understand specifications, proactively identifying and addressing potential design flaws during the development process.
• Analyse verification results, derive insights, and effectively communicate findings and recommendations to stakeholders, contributing to strategic decision-making and project direction.

• B.Sc. in Electrical or Computer Engineering.
• 10+ years of proven experience in VLSI chip Verification engineering, with a focus on high-end SoCs and AI applications.
• 3+ years of proven experience in designing cache systems - an advantage.
• Excellent analytical and communication skills, with the ability to effectively collaborate with cross-functional teams in a fast-paced environment.
• Strong motivating and mentorship.
• Strong proficiency in SystemVerilog, UVM, and other verification tools.
• Experience with AI-specific performance benchmarks, NoC performance benchmark and optimization techniques - an advantage.
• Knowledge of system-level scenario analysis and modelling for high-performance SoCs - an advantage.
• Experience with scripting languages (e.g., Python, Perl) for automation and data analysis - an advantage.

Role Description:

• B.Sc. in Electrical Engineering or Computer Engineering.
• At least 10 years of proven experience in Block Level design.
• At least 3 years of proven experience in Cache systems.
• Backend-RTL relevant skills: solving timing paths, restructuring components, area reduction.
• System Verilog – must.
• Soft skills like communication, teamwork, Ownership, accountability , etc.
• Strong analytical and problem-solving skills.

What You’ll Do:

• Lead physical design from RTL to GDSII for high-performance CPU blocks.
• Own key design flows: synthesis, floor planning, place & route, STA, CTS, power/noise analysis.
• Drive timing closure and ensure final signoff (STA, IR drop, DRC/LVS, equivalence, etc.).
• Optimize power, performance, and area (PPA) for next-gen products.
• Innovate design methodologies and mentor junior engineers.

• Bachelor’s or master’s in electrical/computer engineering (or equivalent).

• 15+ years in structural/physical design using EDA tools (Cadence, Synopsys, etc.).
• Deep expertise in physical implementation, verification, and PPA optimization.