Principal Pcb Package Co-design Engineer jobs at Arm in United States, Chandler

• Cooperate with software teams to establish and implement quality processes at every stage of the development cycle.
• Develop automated test cases for firmware and Linux-based systems (bootloaders, kernel, device drivers and applications).
• Drive improvement at every step of the process in a CI/CD environment.
• Facilitate the timely and effective resolution of any issues detected.

• You will build automated test solutions to deliver production quality software alongside established teams working on our open-source software stack for embedded devices.
• You will contribute to improvements in tooling and automation of various types of testing.
• You will join a distributed team that leads validation efforts to enable the delivery of high-quality software for our new products.

• Good understanding of testing principles, strategies and techniques.
• Experience with integration and system validation tests in an automated environment.
• Proficient user of version control, test management and issue tracking tools.
• Experience at the HW/SW interaction layer, with embedded systems, boot loaders, Linux kernel or device drivers.
• Programming skills to write effective test cases in C and test orchestration in Python.

• ISTQB foundation level certification.
• Experience with functional or non-functional security testing.
• Proficient working with Git, Jira, Yocto.
• Knowledgeable in computer architecture and microarchitecture concepts - ideally for the Arm architecture and its ecosystem.
• Curious about open-source and agile development practices.

As a hardware design engineer, you will be involved in the design process of solutions for different markets by integrating the latest Arm IP products with the target to reach maximum efficiency in terms of power consumption, performance and area while ensuring correct functional behaviour. Your key responsibilities will include creating plans, defining the microarchitecture of the products, developing system level RTL code using System Verilog in a low power context, running design checks, identifying and fixing bugs. Collaboration with functions such as architecture, verification, performance analysis, power analysis, implementation and various IP teams is essential as we work together on enabling our partners' success.

• You graduated from a University or Engineering School, in Computer Science, Mathematics, Electronic / Electrical Engineering, or other related
• Thorough understanding of SoC / ASIC (or FGPA) design methodologies and techniques
• Experience in micro architecture and RTL design using Verilog, System Verilog with a focus on low power design for complex SoCs / ASICs
• Proficiency in both written and oral English

• Knowledge of UPF and experience in low power RTL development constraints is considered an asset
• Experience of working with any of the protocols like PCIe / Ethernet / CAN / DDR / HBM / UFS / eMMC / SDIO is an advantage
• Basic scripting languages, e.g. Perl/TCL/Python
• Knowledge of hardware verification techniques

You will work directly with engineers across the company to build next-generation systems having access to the latest technology. You will have a direct impact on our bottom line and the ability to deliver improvements for our customers. You will be part of a growing, fast-paced, and fun team. You will have ownership for the implementation of your work. Our Sophia office offers a friendly and high-performance work environment.

Collaborate with hardware design teams across multiple projects to develop complex and innovative designs, from consideration of mechanical and thermal requirements, footprint creation and component placement to optimising power planes and routing of high-speed parallel and serial signals. Finalise designs to deliver production data packs (ODB++, Gerber, Fabrication and Assembly drawings and BOMs). You will utilise and develop your skills to design PCBs for complex compute platforms to meet the requirements of the project team and our customers whilst ensuring optimal performance and manufacturability.

• Experience of designing complex, impedance controlled multi-layer (>20), conventional and HDI PCBs with very high pin count devices (>2000), high-speed interfaces (PCIe and DDR), differential pairs, including accommodating high-current PDNs
• Experience of working alongside a chip packaging team. Able to influence and advise on pinout and routing topologies of SoC's or complex FPGA devices, cost optimisation, routing feasibility and layer trade-off analysis
• Detailed knowledge of escape routing of high density SoC's, FPGAs, able to provide estimates of the IO count that can be routed with a particular stack-up and rule set
• Appreciation of Signal Integrity and Power Integrity as applicable to routing strategies
• Extensive knowledge of the PCB fabrication process (conventional and sequential), IPC standards and stackup topologies, substrate materials, via structures, etc
• Proficient in the use of EDA Tools, specifically Cadence OrCAD CIS, Allegro PCB suite, Mentor PADs Layout.
• Ability to collaborate with PCB fabricators and CEMs for DFM/DFT and automated assembly. Ensure designs are aligned with supplier capabilities and best practise
• Good interpersonal skills. Participate in reviews, providing advice to engineers relating to design rules, PCB fabrication and substrate technologies

• Certified Interconnect Designer (CID, CID+)
• Experience with version control systems (e.g. SVN)
• Experience of automating: decoupling capacitor optimisation, IC placement optimisation, drawing templates etc.

You will gain a deeper understanding of high-performance compute platforms. Work alongside other engineering teams including hardware, packaging, SoC implementation, collaborating and enabling engineers and designers. You'll be working with highly talented and motivated colleagues in a friendly supportive environment. Extending your board level design expertise, producing high quality PCB designs incorporating Arm IP, you will enjoy new technical challenges faced when using advancing technologies!

• Engage with technical leads, product managers and SoC development teams to translate technology requirements into platform architectures
• Work proactively across Arm’s architecture and core technology groups, taking ownership over the full product lifecycle
• Evaluate different architecture proposals and features and coordinate across SoC, hardware, software and platforms to align all parties to a common vision, supporting the needs of Arm based embedded device SoCs
• Be central to the involvement in new and different activities at different times as needed, as we are involved in a broad cross-section of engineering across the project lifecycle
• Create high level architecture specifications to enable engineering teams to craft and verify platforms addressing the embedded device, compute and IoT market segments
• Communicate technical concepts clearly and credibly across audiences ranging from individual hardware and software engineers to architecture peers and technology leads

• Experience in Electrical or Electronic Engineering, Computer Science or related field
• Deep technical background and solid understanding of SoC architectures involving embedded compute, CPUs, IoT space, AI or related work experience
• Experience with various high-speed IO interface standards (e.g. PCIe and DDR) and peripherals for embedded storage and compute
• Competence with embedded system board design, designing with complex LSI devices such as FPGAs and embedded firmware
• Ability to drive progress in an ambiguous environment with evolving needs
• Ability to work optimally in a fast-paced environment with changing priorities and requirements
• Excellent communication and interpersonal skills with the ability to coordinate across multiple teams. Collaborative and influential across organizations and geographies

• Fundamental understanding of compute architectures and functional building blocks
• Experience working within the semi-conductor industry

DDR Subsystem Architect is a technical role responsible for hardware architecture of LPDDR, DDR, HBM and GDDR subsystems for high-volume, sophisticated, SoC platforms on groundbreaking process nodes across multiple market segments including mobile, automotive, datacenter and networking, and IoT.

• Consume JEDEC specs and DRAM vendor roadmaps to create product intercept roadmaps.
• Work with SoC architects, business-units, and customers to establish & reconcile DDR subsystem features & requirements.
• Author architectural specifications to a mature stage allowing design and implementation teams to engage actively.
• Work with IP vendors to draft, negotiate, and execute SoWs/contracts.
• Work with design, verification, and validation teams to draft and review design specifications & test-plans (pre & post silicon), and support execution teams as required.
• Debug performance and functional issues with high-level models, RTL simulation, hard and soft IP.

• Deep understanding of DDR controller design and memory types (LPDDR, DDR, HBM, GDDR).
• Experience with controller-to-PHY interface protocols (DFI).
• Familiarity with Arm bus protocols such as APB, AXI, CHI, CXS, etc.
• Experience with performance/QoS, RAS, security, power-management, debug, and test features in the context of DDR subsystems.
• Bachelor's or Master’s degree in Electrical or Computer Engineering with minimum 10 years of experience in a senior development position.
• Excellent presentation, interpersonal, written, and verbal communication skills.

Arm is proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work collaboratively to defy ordinary and shape extraordinary!

• Partner and customer focus
• Collaboration and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises

• As a creative verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, PCIe/CXL, DDRx/LPDDRx integration verification in SoC RTL.
• You will work with the project team to understand and review the architecture and design specifications, and to build a functional verification strategy.
• Your key responsibilities will include crafting test plans, developing SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues.
• You will also contribute to developing and improving the verification methodologies used by the team.
• In addition, you'll work closely with other teams on the design microarchitecture, verification methodologies, system performance, etc.
• You will balance other opportunities such as working with Project Management on activities, plans, and schedule as well as guide and support junior members of the team.

In addition to bringing your accomplishment of either Bachelors or Master’s degree in Computer Science or Electrical/Computer Engineering (or similar field) over 5+ years of experience working in design or verification of sophisticated compute subsystems or SoCs, you will need:

• Solid understanding of digital hardware design and Verilog HDL.
• A detailed understanding and experience of the current verification strategies required for sophisticated SoC development, including software-based techniques
• Experience verifying subsystems for PCIe/CXL, DDRx/LPDDRx, HBM
• Good knowledge of test plan creation and tracking
• Experience verifying RTL for SoC projects
• Low-level programming experience including C and Assembler

• Experience with Arm-based designs and/or ARM System Architectures
• Experience with SystemVerilog and verification methodologies – UVM/OVM/e
• Experience or knowledge in the following areas
• Formal verification techniques
• Clock domain crossing verification
• Experience with Perl, Python or other scripting language
• Power aware verification
• Porting peripheral driver software
• Development and deployment of sophisticated Arm SoCs on multiple Emulation platforms as well as direct hands-on test bench development.

We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together. These behaviors are assessed as part of the hiring process:

• Partner and customer focus
• Collaboration and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises

We offer a hybrid approach to home and office working to provide an adaptable experience for all employees. We expect some working time to be spent in office, to promote a strong collaborative environment with good team integration but are accommodating to different home working requirements.

• Travel across Europe and the UK, supporting our partners in the games industry in their use of Arm technology
• Collaborating closely with your counterpart team in China to share knowledge
• Keeping up to speed on the latest graphics techniques, learning from other teams within the company
• Sharing lessons learned and providing feedback to our research and tooling development teams, driving our future roadmaps

• Understanding of modern Game Engine rendering pipelines
• Ability to debug and modify graphics features
• Graphics profiling knowledge
• Modern graphics API knowledge (Vulkan, DirectX12)
• Shader development and optimization skills
• Excellent communication and collaboration skills
• The ability to integrate yourself as a guest in a new team and share your knowledge while respecting the domain and skills of the team you are advising
• High debugging skills for both CPU and GPU
• Experience in working with large codebases, both adding features and maintaining
• Programming experience (C++ and shader languages)
• Experience with version control system and delivering software.

• Shader development and optimisation skills
• Debugging skills for both CPU and GPU
• Experience in working with large codebases, both adding features and maintaining
• Knowledge of emerging AI graphics techniques
• Games proven experience, ideally as part of an engine / CoreTech team
• Familiarity with CI pipelines and validating / testing the codebase