דרושים Senior System Software Engineer Gpu Development Tools ב-אנבידיה ב-India, Karnataka, Bengaluru

What you will be doing:

• Lead design and development of NVIDIA’s Assembler and Disassembler for GPU compute.

• Work on binary analysis & instrumentation features like call graphs generation, program register usage and patching of GPU binaries

• Work with GPU architecture and debugger/profiler development teams to understand their requirements and deliver new features & product improvements.

• Collaborate closely with teams developing other related components to ensure compatibility, reliability, and high-quality code generation

• Working with customers/partners to collect feedback and drive innovative ideas and features to incorporate into the product

What we need to see:

• BS or MS degree in Computer Science, Computer Engineering, or related fields with 5+ years of experience in low-level system SW development and a minimum of 3 years related to assemblers, binary analysis tools, debuggers

• Good analytical and C/C++ programming skills

• Experience in any one area of compiler development including feature support, code generation and compiler infrastructure

• Understanding of Assembly Language / Processor ISA (GPU ISA not required but a plus)

• Knowledge of object file formats such as ELF and debugging formats (DWARF).

Ways to stand out from the crowd:

• Understanding of debugger / profiler tools / bintools / Linker internals, experience in binary analysis / instrumentation tools like BOLT etc.

• Usage of AI tools in everyday work like Cursor, Windsurf etc.

• Knowledge of GPU development and compute APIs such as CUDA and OpenCL

What you'll be doing:

• Enable NVIDIA Cumulus Linux on next generation ASICs.

• Define, design and develop features for NVIDIA Cumulus Linux.

• Sustain the existing deployments of NVIDIA Cumulus Linux.

• Working closely with customers to understand the pain points, new use cases, deployment strategies and come up with innovative solutions.

• Translating requirements to the SDK and ASIC Engineers for enabling end-to-end solutions.

What we need to see:

• Strong knowledge of forwarding path for L2 and L3 including concepts like ECMP etc.

• Strong and proven experience in C and Python programming.

• Worked with VxLAN and EVPN routing protocols.

• Strong knowledge in areas of QoS, ACLs and VxLAN. And working knowledge of hardware resource management (tables, TCAMs, etc).

• Battle scars from troubleshooting production network deployments.

• BS or MS degree in Computer Engineering, Computer Science, or related degree, or equivalent experience.

• 5+ years of hands on experience.

Ways to stand out from the crowd:

• Experience with Merchant Silicon for Switching/Routing.

• Contributions to SONiC, SwitchDev or Switch Abstraction Interface (SAI) projects.

What You’ll Be Doing:

• Develop and maintain robust equivalence checking flows (FEC/FEV) for different stages of the VLSI design cycle, including RTL-to-RTL, RTL-to-Gate, and Gate-to-Gates equivalence checking.

• Develop and enhance the RTL Physical-Synthesis work flows, both at full-chip and block-level.

• Partner with implementation teams, on both synthesis and P&R side, to understand their requirements and pain-points if any, and enhance the methodology to cover for the same.

• Develop and deploy various methodologies based on technology updates, design requirements, and tool-feature/version updates and bug-fixes.

• Finetune the recipes for designs with aggressive PPA targets while ensuring logical-equivalence is maintained.

• Optimize flows and methodologies for performance, capacity, and debug capabilities, ensuring efficient and effective verification of sophisticated VLSI designs.

• Investigate and resolve equivalence checking issues, including setup and constraint-related problems, debug failures, and performance bottlenecks.

• Develop custom scripts using tcl/perl/python to automate the post-processing of the reports/logs to present the results in a user-friendly format.

What We Need To See:

• B.Tech/BS inVLSI/Electronics/ElectricalEngineering or Computer Science, with 5+ years of relevant ASIC design experience and/or CAD experience, with a focus on Logic Equivalence Checking and RTL-Synthesis.

• Be familiar with Verilog and ASIC design flow along with experience in commercial EDA tools

• Strong scripting skills in languages such as Perl, Python, and TCL.

• Excellent problem-solving, debugging, and analytical skills.

• Ability to work in a team environment and collaborate efficiently with multi-functional teams.

• Strong communication and documentation skills

What you'll be doing:

• Lead a team involved with development and delivery of Cumulus Linux packet forwarding andinfrastructurefeatures. Partner with other engineering teams to scope and develop solutions to improve systems security, performance and reliability features.

• Lead a team to design, develop, test and maintain new functionality and improvements to existingfunctionalityrelated to packet forwarding and offload of L2, routing, ACLs, NAT, policy-based routing,VxLAN-EVPN.

• Develop and debug C and Python code for packet forwarding monitoring, reliability and serviceability features as needed.

• Collaborate with product, architecture, and engineering teams for End to End integration of systems infrastructure features into Linux and Cumulus Linux distribution

• Work with project management team for effort estimation and planning of the features.

• Work closely with recruiting staff to expand the team, including sourcing and interviewing candidates, participating in conferences/events, and onboarding new employees. Help engineers develop their careers, assigning them to projects tailored to their current skill levels as well as their long-term development, taking into account evolving strengths and capabilities

• Work with upstream communities as needed, supervise technology trends like emerging standards for any technology opportunities.

• Guide through the problem solving process, minimize how often problems take place and proactively take steps to prevent problems from happening

What we need to see:

• Master of Science in Electrical Engineering, Computer Science, Computer Engineering or Bachelors (or equivalent experience)

• 10+ overall years of proven leadership in Linux systems, data center networking technologies; familiarity with datacenter protocols and 5 or more years of people management experience in an enterprise environment.

• Familiar with cloud native concepts

• Strong background with Linux OS feature development

• Experience driving projects from concept to production

• Excellent written and verbal communication and interpersonal skills. Comfortable articulating value propositions to customers and influencing internal teams

• Experience with embedded software on network switches.

• Background with bring up and troubleshooting of Ethernet Switching ASICs, Ethernet interfaces and modules

Ways to stand out from the crowd:

• Strong background in Ethernet switching, Linux systems and Linux kernel networking

• Experience with Merchant Silicon based platforms for Switching/Routing

• Contributions to SONiC, SwitchDev or Switch Abstraction Interface (SAI) projects.

• Knowledge of networking control plane operation in areas like IP, EVPN, Segment Routing etc.

What you'll be doing:

• You are encouraged to understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through agile framework

• Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.

• Work on SOC Assembly and drive cross-functional teams towards SOC milestone execution.

• Be responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification atcluster/sub-system/SOC/emulationlevels.

• Have good grasp of Perl, Python, or other industry-standard scripting languages.

What we need to see:

• BS (or equivalent experience) / MS with 5+ years of practical semiconductor design and architecture experience building complex SoC’s.

• Must have firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design.

• Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).

• C/C++ programming or python or any other industry-standard scripting language experience desirable.

• Experience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.

• Hands on experience in successful tape outs of multiple complex, high-volume SoCs in advanced process nodes.

• Exposure to various Chip Design Functions to be able to collaborate and solve complex cross functional problems.

• Experience in synthesis, physical design and DFT is a plus & Experience in RTL Build and Design Automation is a plus.

Ways to Stand out from the crowd:

• Chip lead type of technical leadership experience on delivering complex SOCs for enterprise and/or HPC applications.

• Experience in RTL coding and debug, as well asperformance/power/areaanalysis and trade-offs

• Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.

• Prior experience of smartNIC and/or high-speed interconnect, strong coding skills in Perl, Python, or other industry-standard scripting languages.

• SOC bring-up and post silicon validation experience