As a Static Timing Engineer, you will be spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints.You will also closely collaborate with RTL designers to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical Design team to close and sign-off timing. You will come up with ideas and plans to verify your own timing constraints, innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fallouts in timing analysis.