דרושים Taiwan, Taiwan Province, Hsinchu

What you’ll be doing:

• A senior role in physical design for NVIDIA GPU and Mobile chips.

• Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification. Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention.

• Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.

What we need to see:

• BS in Engineering or Science or equivalent experience

• Power user of EDA tools from Synopsys(ICC2/DC/PT/STAR-RC),Cadence (EDI/Innovus/Voltus) or Ansys (Redhawk)

• Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes

• 2+ years of experience in above areas

Ways to stand out from the crowd:

• MS in Engineering or Science

• Knowledge in FinFET technology, circuit design, and package design

• Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre)

• Proficiency in Perl, Python, TCL and Makefile scripts

What you'll be doing:

• Sustain the test program of mature products and released it into the production line successfully

• Driving the factory key performance index & metrics measurement for periodic review

• Working with the subcontractors for continuous process improvement

• Collaborate the engineering activities with the functional team and the subcontractor

• Managing the manufacturing, engineering and quality issues on the production line

• Identifying and fixing manufacturing problems

• Identifying and fixing the process, material and test program issues

What we need to see:

• Master Degree in Electrical/Computer Engineering or Computer Science

• Familiarity with mixed-signal IC design or interested in IC test field

• Familiarity with IC manufacture process or interested in IC production management

• Familiarity with the programming (C/C++)

• Familiarity with the Microsoft office and data analysis tool

• Strong communication skills in both English and Mandarin

• Self-motivated and able to work effectively across different functional teams and subcontractors

• Good communication and organization skills, with a logical approach to problem solving

What you'll be doing:

• Verify the design and implementation of the industry's leading GPU

• Responsible for verification of the Mixed Signal CMOS circuit design, architecture, golden models using advanced verification methodologies

• You are expected to understand complex mixed-signal CMOS circuits design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.

• Work closely with Multi-functional teams, circuit and logic design, verification, test engineering to accomplish tasks.

What we need to see:

• Pursuing MS/PhD in EE with domain study in analog circuit design / mixed signal circuit design.

• Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like HSpice, Finesim, XA)

• Experience in crafting test bench environments for component and top level circuit verification

• Expertise in System Verilog or similar HVLand strong debugging and analytical skills

• Perl and C/C++ programming language experience desirable

• Strong communication skills and ability & desire to work as a great teammate are huge plus.

What you'll be doing:

• Be part of an analog team developing high-speed chip interfaces and complex analog functions that enable our graphics processing units (GPU) and SoC products (Tegra)

• Design state-of-the-art mixed-signal circuits in deep sub-micron CMOS technologies.

• Work closely with physical/layout engineers to floorplan and implement physical design of these functions.

• Support debug, characterization and support product through high-volume production.

• If you have the dream to learn and explore new technologies and have good analytical skills, this is the ideal position for you.

What we need to see:

• You have a MSEE or PhD in Electrical Engineering.

• Proven understanding of analog circuit layout concepts in submicron CMOS technologies

• You have interests in more than one of the following areas: digital links for display interfaces (such as HDMI, LVDS, DVI, MIPI PHY, Display Port), USB, low-jitter clock synthesis using PLL techniques, IO pads, high-speed serial links, and ADC.

• Able to communicate in spoken and written English

• Work effectively in a team, good communication skills, enthusiasm and positive energy.

• Proficiency in scripting languages like perl, python, skill etc.

• Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like HSpice, Finesim, XA)

• You are an expert with Cadence custom circuit design tools - particularly virtuoso

• Experience running and debugging DRC and LVS with verification tools