

What You'll Be Doing:
Post-layout model extraction for project review sign-off
pre-layout model extraction for DOE
Work closely w/ Package and PCB Design teams to design and ensure link performance meets expectation before tapeout
Develop novel algorithms & new methodologies to improve SI/PI/EMI modeling efforts
Work w/ Application Engineering teams to support customers w/ SI/PI questions
Support signal integrity simulation and analysis for interfaces PCIE, NVLink, display, LPDDR etc.
What We Need To See:
MS in EE and majoring in SI/PI technology
Strong understanding of electromagnetics, specifically electromagnetic waves including transmission line theory and via properties, and the SI/PI/EMI applications; S/Y/Z parameters; discrete signal processing knowledge
Know how to use ANSYSHFSS/Q3D/SIwave/Designer,Synopsis HSPICE, Cadence PowerSI, and Keysight ADS
Understanding of high-volume manufacturing variations and impact to channel signal integrity is a plus
Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design , and equalization schemes
Familiarity with transient simulation in tools and understanding of eye diagram methodology
Exposure to lab measurements including VNA & TDR, and oscilloscope experience
Passionate about SI/PI work
Ways To Stand Out From The Crowd:
SI analysis flow including frequency and time domain simulation
PDN analysis flow including model generation and time domain simulation
PSIJ Analyses involving co-simulation of circuits and PDN models
Experience w/ Matlab, Python, VBS, and C
RF/microwave engineering; EMI/RFI analysis capability
משרות נוספות שיכולות לעניין אותך

What you will be doing:
Work closely with other HW engineering teams such as silicondesign/characterizationteams, IO design/validation teams, system feature owners, operations to determine coverage needs and constraints to resolve appropriate test conditions, diagnostic contents for production line screen.
Define requirements to SW and board teams to support/improve test infrastructure, debug knobs and data collection features needed to support manufacturing screens effectively.
Craft creative solutions and workarounds through volume data analysis and lab experimentation to solve challenging yield and test problems seen in production.
Lead optimization and continuous improvement efforts on the production screen spec definition processes to minimize waste and meet test time, yield, DPPM requirements.
Support customer facing and quality teams during customer escalations to understand the issue and fix gaps identified in coverage.
Define procedures to facilitate correlation activities between production testing infrastructure and internal diagnostic programs.
Create key performance indicators used to evaluate the effectiveness of the new tests.
What we need to see:
BS or MS degree in EE/CE, or equivalent experience.
5+ years of relevant industry experience.
Strong EE fundamentals, knowledgeable in digital design, signal integrity, statistics, timing analysis, fault analysis, sampling and computer architecture.
SLT experience. Strong data analysis skills. Prior experience working with volume data is a plus.
Validated hands-on lab experience with silicon bringup and lab debug.
Good understanding of firmware/driver structures and their interaction with HW.
Problem solving, debugging, analysis and logical reasoning skills with examples to prove it.
Experience with Python, BASH, Linux.
Ways to stand out from the crowd:
Deep understanding of technology and passionate about what you do.
Familiarity with statistical methods and tools for data analysis.
Strong collaborative and communication skills, specifically a shown ability to effectively guide and influence within a dynamic environment.
Strive to be a standout colleague and be ready to work with global teams from diverse cultural backgrounds in a high energy environment.

What you’ll be doing:
Study and develop data analytics, and perform in-depth analysis and optimization to ensure the best possible performance on current and next-generation GPU architectures.
Work directly with key customers to understand the current and future problems they are solving.
Collaborate closely with the architecture, research, libraries, tools, and system software teams at NVIDIA to influence the design of next-generation architectures, software platforms, and programming models.
What we need to see:
BS degree from university in an engineering or computer science related discipline (MS or PhD preferred).
Expert mathematical fundamentals, including linear algebra and numerical methods.
Strong knowledge of Fortran and/or C/C++.
Good communication and organization skills, with a logical approach to problem solving, good time management, and task prioritization skills.
Experience with parallel programming, ideally OpenACC and CUDA C/C++.

What you'll be doing:
Develop automation test infrastructure-based data center
Work closely with AI infrastructure engineer to develop FW/OS feature testing
Strong ability to work independently, given requirements
Strong Linux development and debugging experience
Demonstrable comprehension of Information Security, including malware, emerging threats, charges, and vulnerability management
What we need to see:
Master’s degree in computer science or electrical engineering
Experienced in effectively bringing to bear AI and knowledgeable in CI/CD tools
Strong Python/C++ programming skills
Excellent communication and social skills
Excellent data analysis skills and the ability to resolve issues involving sophisticated systems
Good at English read/write/speak

What you'll be doing:
Principles of hardware operation: CPU and memory architecture, buses and interconnects
Operating System fundamentals: multi-processing and scheduling, memory management, privilege modes, file systems and device drivers
Algorithms and data structures
C and/or C++ programming languages
Python knowledge is preferred
What we need to see:
Strong academic background
MS or BS in Electrical Engineering, Computer Engineering or Computer Science
Good understanding of programming languages and processor architecture
Good understanding of Operating System Fundamentals.
Knowledge of Windows kernel is a plus
Strong C/C++ programming skills
Knowledge of scripting (python/javascript) is a plus
Candidates should have a solid background in
Operating System, Algorithm development
Aptitude in innovative and optimal design
Ways to stand out from the crowd:
Exposure to Digital Systems, Computer Architecture, Computer Arithmetic, Software Eng., C & C++ programming languages, assembly language programming, system level integration & system level programming is preferred.
Problem solver and Good communications skills and ability to work independently and desire to work as a team player are a must.

What you’ll be doing:
Verify our custom IP macros.
Collaborate with Design, Integration and TE teams to determine verification scope, develop strategies, implement test planning, and verify designs at IP level, cluster level, and full chip level
Collaborate with CAD team to optimize & smooth our simulation flow
Generating testpatterns and perform silicon bring-up
What we need to see:
Master degree of Electrical Engineering/Computer Engineering/Computer Science
Strong debugging and analytical skills with RTL/Gate-level design tracing(Verdi) and verification simulation tool(VCS).
Familiarity with SOC basic architecture (clock, reset, power rail, IO pad, package)
Understanding of Design for Testing including Scan/ATPG/BIST/JTAG is a plus
Skills ofPython/Perl/Tck/C/C++is a plus
Ways to stand out from the crowd:
Fluent English communication is required

What you’ll be doing:
Designing, implementing, and delivering innovations for managing GPU based AI servers with focus on OOB management, firmware development, server architecture and building systems for enterprise.
Working with a global team of BIOS developers on NVIDIA server designs.
Designing and developing performance optimized UEFI/BIOS solutions using industry Standards.
Instrumenting code to ensure maximum code coverage, writing and automating unit tests for each implemented module and maintain detailed unit test case reports.
Providing software quality reports based on static analysis, code coverage, CPU load.
Working with security team to ensure developed code is in line with product security goals.
Partner closely with hardware teams to influence hardware design and review HW architecture & schematics.
Working with QA/Test architects to come up with proper test tools and automation for qualifying the whole system software and firmware stack.
What we need to see:
Domain expertise in System BIOS (UEFI) Firmware development on X86 or ARM Platforms.
Strong experience with AMI/Insyde or EDK2 Firmware architecture.
Solid experience of end-to-end delivery of high-end enterprise servers from definition to customer deployment.
Solid understanding of low-level interfaces between SBIOS, BMC and OS like I2C/SPI/PCIe/JTAG etc. PCIe enumeration, IO at platform level for enterprise systems.
Strong experience with RAS.
Experience working closely with HW teams, ODMs and vendors to introduce and support server platforms.
Experience with C/C++ development, bash/python for scripting, and debugging skills in embedded Linux operating environments.
You should possess excellent written and oral communication skills, good work ethics, high sense of team-work, love to produce quality work and commitment to finish your tasks every single day. You are a self-starter who loves to find creative solutions to exciting problems.
Bachelor’s Degree or higher; in Electrical Engineering or Computer Science, and 8 years of experience, with demonstrated strong ability as individual contributor.
Ways to stand out from the crowd:
Proven record in delivering system BIOS design on servers
Experience working with AMI/Insyde BIOS solutions on x86 designs.

What You'll Be Doing:
Post-layout model extraction for project review sign-off
pre-layout model extraction for DOE
Work closely w/ Package and PCB Design teams to design and ensure link performance meets expectation before tapeout
Develop novel algorithms & new methodologies to improve SI/PI/EMI modeling efforts
Work w/ Application Engineering teams to support customers w/ SI/PI questions
Support signal integrity simulation and analysis for interfaces PCIE, NVLink, display, LPDDR etc.
What We Need To See:
MS in EE and majoring in SI/PI technology
Strong understanding of electromagnetics, specifically electromagnetic waves including transmission line theory and via properties, and the SI/PI/EMI applications; S/Y/Z parameters; discrete signal processing knowledge
Know how to use ANSYSHFSS/Q3D/SIwave/Designer,Synopsis HSPICE, Cadence PowerSI, and Keysight ADS
Understanding of high-volume manufacturing variations and impact to channel signal integrity is a plus
Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design , and equalization schemes
Familiarity with transient simulation in tools and understanding of eye diagram methodology
Exposure to lab measurements including VNA & TDR, and oscilloscope experience
Passionate about SI/PI work
Ways To Stand Out From The Crowd:
SI analysis flow including frequency and time domain simulation
PDN analysis flow including model generation and time domain simulation
PSIJ Analyses involving co-simulation of circuits and PDN models
Experience w/ Matlab, Python, VBS, and C
RF/microwave engineering; EMI/RFI analysis capability
משרות נוספות שיכולות לעניין אותך