דרושים ב-Nvidia ב-Taiwan, Hsinchu

What you’ll be doing:

• A senior role in physical design for NVIDIA GPU and Mobile chips.

• Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification. Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention.

• Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.

What we need to see:

• BS in Engineering or Science or equivalent experience

• Power user of EDA tools from Synopsys(ICC2/DC/PT/STAR-RC),Cadence (EDI/Innovus/Voltus) or Ansys (Redhawk)

• Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes

• 2+ years of experience in above areas

Ways to stand out from the crowd:

• MS in Engineering or Science

• Knowledge in FinFET technology, circuit design, and package design

• Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre)

• Proficiency in Perl, Python, TCL and Makefile scripts

What you'll be doing:

• Sustain the test program of mature products and released it into the production line successfully

• Driving the factory key performance index & metrics measurement for periodic review

• Working with the subcontractors for continuous process improvement

• Collaborate the engineering activities with the functional team and the subcontractor

• Managing the manufacturing, engineering and quality issues on the production line

• Identifying and fixing manufacturing problems

• Identifying and fixing the process, material and test program issues

What we need to see:

• Master Degree in Electrical/Computer Engineering or Computer Science

• Familiarity with mixed-signal IC design or interested in IC test field

• Familiarity with IC manufacture process or interested in IC production management

• Familiarity with the programming (C/C++)

• Familiarity with the Microsoft office and data analysis tool

• Strong communication skills in both English and Mandarin

• Self-motivated and able to work effectively across different functional teams and subcontractors

• Good communication and organization skills, with a logical approach to problem solving

What you'll be doing:

• Verify the design and implementation of the industry's leading GPU

• Responsible for verification of the Mixed Signal CMOS circuit design, architecture, golden models using advanced verification methodologies

• You are expected to understand complex mixed-signal CMOS circuits design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.

• Work closely with Multi-functional teams, circuit and logic design, verification, test engineering to accomplish tasks.

What we need to see:

• Pursuing MS/PhD in EE with domain study in analog circuit design / mixed signal circuit design.

• Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like HSpice, Finesim, XA)

• Experience in crafting test bench environments for component and top level circuit verification

• Expertise in System Verilog or similar HVLand strong debugging and analytical skills

• Perl and C/C++ programming language experience desirable

• Strong communication skills and ability & desire to work as a great teammate are huge plus.

What you'll be doing:

• Be part of an analog team developing high-speed chip interfaces and complex analog functions that enable our graphics processing units (GPU) and SoC products (Tegra)

• Design state-of-the-art mixed-signal circuits in deep sub-micron CMOS technologies.

• Work closely with physical/layout engineers to floorplan and implement physical design of these functions.

• Support debug, characterization and support product through high-volume production.

• If you have the dream to learn and explore new technologies and have good analytical skills, this is the ideal position for you.

What we need to see:

• You have a MSEE or PhD in Electrical Engineering.

• Proven understanding of analog circuit layout concepts in submicron CMOS technologies

• You have interests in more than one of the following areas: digital links for display interfaces (such as HDMI, LVDS, DVI, MIPI PHY, Display Port), USB, low-jitter clock synthesis using PLL techniques, IO pads, high-speed serial links, and ADC.

• Able to communicate in spoken and written English

• Work effectively in a team, good communication skills, enthusiasm and positive energy.

• Proficiency in scripting languages like perl, python, skill etc.

• Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like HSpice, Finesim, XA)

• You are an expert with Cadence custom circuit design tools - particularly virtuoso

• Experience running and debugging DRC and LVS with verification tools

What you'll be doing:

• Be part of an analog team building next generation NVLINK.

• You will be responsible for the development and implementation of high speed interfaces, including TX/RX/Clocking/PLL.

• Work closely with physical/layout engineers to floorplan and implement physical design of these functions.

• Support debug, characterization and support product through high-volume production.

What we need to see:

• MS / PhD in Electrical Engineering, Computer Engineering or related field with strong analog design background.

• CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET); Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA)

• You have interests in more than one of the following areas: digital links for display interfaces (such as HDMI, LVDS, DVI, MIPI PHY, Display Port), USB, low-jitter clock synthesis using PLL techniques, IO pads, high-speed serial links, and ADC.

• Able to communicate in spoken and written English

• Work effectively in a team, good communication skills, enthusiasm and positive energy.

• Proficiency in scripting languages like perl, python, skill etc.

• You are an expert with Cadence custom circuit design tools - particularly virtuoso

• Experience running and debugging DRC and LVS with verification tools

What you'll be doing:

• Mixed-Signal/Analog circuit design for High-Speed Memory I/O Interfaces

• Develop and implement high speed interfaces and analog circuits using the latest CMOS FinFET processes

• Help define circuit requirements and complete design from schematic, layout, and verification to characterization

• Optimize design to meet the specifications for system performance.

What we need to see:

• MS in Electrical Engineering, PhD is preferred.

• TX/RX related design experience or is fairly familiar with high-speed SerDes/analog circuit design concepts

• CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET)

• Strong background of Cadence custom design tools, various circuit simulators like Hspice, XA, FineSim, Spectre

• Experience in crafting test bench environments for component and top level circuit verification

• Knowledge of Verilog, Verilog-A, Matlab, or similar tools for behavioral modeling of analog and digital circuits is a plus

• Strong debugging and analytical skills

• Strong interpersonal skills and ability & desire to work as a good teammate

We are looking for a Digital Circuit Design Intern. As a member of our Mixed-Signal high-speed I/O SerDes group, you'll be working on NVDIA's latest ground breaking technology that enables and accelerates gaming, artificial intelligence, deep learning, and autonomous driving. Your design will be consumed by standard as well as industry-leading proprietary high-speed protocols, and will serve as one of the key IPs in many complex SoC. You'll work closely with analog designers and system architects to independently come up with micro-architecture specification and refine adaptation algorithms. You'll then implement the RTL in SystemVerilog, define test cases that will deeply verify the design and carry out test creations. Next is to define and build constraints for synthesis and drive for timing closure. In addition to RTL design, you'll need to understand the analog schematics and write SystemVerilog models that collects the functionality of those circuits in the most precise way.

What you'll be doing:

• Be actively involve in developing mixed-signal chips .

• Plan the specification, evaluate the PPA of algorithms, design the digital circuits such as filters and analog calibration circuits

• Verify the analog and digital design using direct test and random test

• Perform the frond-end design flows(Lint/CDC/Synthesis/DFT/LEC/STA)and co-work with back-end team to chip tape-out

• Help in silicon bring-up and fine-tune performance

What we need to see:

• Pursuing Master / PhD in Electrical Engineering.

• Solid understanding or experiencein high-speed SerDes I/O digital design, knowledge at protocol level (Ethernet, PCIE) preferred.

• Have a deep understanding of Verilog or SystemVerilog, logic design and circuit modeling in RTL for mixed-signal blocks; Experience with industry standard verification methodologies, such as UVM.

• Knowledge with custom digital circuit design and adaptation algorithms, such as FFE, DFE, CTLE, CDR, and offset cancellation.

• Familiar with static timing tools and formal verification tools.

• Have a strong background in Perl and Python scripting; If you have a background in computer architecture and deep learning, this is a plus.