דרושים Cpu-soc Mask Layout Designer ב-אינטל ב-מלזיה

Performs Pre-Silicon functional verification of CPU logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to CPU microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design and uncover bugs. Replicates, root causes, and debugs issues in the Pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with CPU architects/RTL developers to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology.
Qualifications:

• Bachelor's or Master's degree in Electrical or Electronics Engineering, Computer Engineering, or any related field.
• Good knowledge in CPU architecture and Computer System
• Experience with System Verilog and UVM.
• Experience with scripting (i.e PERL, Phyton)
• Familiar with verification tools and methodologies.
• Good problem-solving and debugging skills.
• Effective communication and collaboration abilities.
• Self-motivated and able to work effectively in a dynamic, fast-paced environment.

Shift 1 (Malaysia)Malaysia, Penang

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Qualifications:

You must possess a minimum of Bachelor Degree inElectrical/ElectronicsEngineering or Computer Engineering.

Additional qualifications include:

• Knowledge of Computer System Architecture.
• Knowledge in digital logic design, pre-silicon or post-silicon validation.
• Experience in tools and methodologies for pre-silicon verification/logic design including but not limited to: System Verilog, PERL/C/C++ programming, Synopsys simulator will be big plus.
• Strong analyzing and debugging skill, creative in problem solving.

Shift 1 (Malaysia)Malaysia, Penang

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

In this position, you will be involving in the training, design and development of next generation SOC/CPU for wide range of Intel products. Your responsibilities will include some of the following but not limited to:- Creates mask layouts of integrated circuits for a given specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts. - Creates accurate designs that meet project needs, applying understanding of design manuals, established processes, layout elements, and basic electronic principles. - Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. - Designs and analyzes floorplans, power grid, and bumps and performs all required verification on the layout blocks. - Troubleshoots a wide variety of issues up to and including layouts andused in layout design.You must possess the below minimum qualifications to be initially considered for this position:- Diploma in Electronic and Electrical Engineering or related major with good CGPA. - Good communication skills and proficient in English- Knowledge on Unix, VLSI Design, SOC/PC Architecture, System Verilog is major plusShift 1 (Malaysia)Malaysia, Penang

Develops pre-silicon functional validation test suites to validate system will meet design requirements and delivering state-of-the-art chipsets/SoC validation on the next generation design.
Creates test plans, defining, executing and debugging on system emulation models, and finding and implementing corrective measures for failing test.- Bachelor/Masters in Computer/Electronic Engineering
- Knowledge on Computer System Architecture and/or related software-hardware sub-systems.
- Experience with software programming in Python, C and/or C++ language.
- Experience ondebug, or RTL validation is a plus.- Highly motivated, curious, and keenly interested in finding and resolving technical anomaliesShift 1 (Malaysia)Malaysia, KulimMalaysia, Penang

Job Description:

• Performs Pre-Silicon functional verification of CPU logic to ensure design will meet specification requirements.

• Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to CPU microarchitecture specifications.

• Executes verification plans and defines and runs system simulation models to verify the design and uncover bugs.

• Replicates, root causes, and debugs issues in the Pre-silicon environment.

• Finds and implements corrective measures to resolve failing tests.

• Collaborates with CPU architects/RTL developers to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.

• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.

• Maintains and improves existing functional verification infrastructure and methodology.

Qualifications:

• Bachelor's or Master's degree in Electrical or Electronics Engineering, Computer Engineering, or any related field.

• Good knowledge in CPU architecture and Computer System.

• Experience with System Verilog and UVM.

• Experience with scripting (i.e PERL, Phyton).

• Familiar with verification tools and methodologies.

• Excellent problem-solving and debugging skills.

• Effective communication and collaboration abilities.

• Self-motivated and able to work effectively in a dynamic, fast-paced environment.

Experienced HireShift 1 (Malaysia)Malaysia, Penang

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including BSCAN).
• Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, BSCAN, proc monitors, in system test/BIST).
• Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
• Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block. Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
• Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
• 5+ years of experience in DFT, SOC design, or related semiconductor design areas. Strong knowledge of DFT techniques, including BIST, boundary scan, JTAG, and fault simulation.
• Experience with EDA tools for DFT (e.g., Synopsys DFT Compiler, Mentor Tessent, Cadence Modus, ATPG).Proficiency in hardware description languages such as VHDL, Verilog, or System Verilog.
• Expertise in automated test generation and analysis tools. Strong problem-solving skills with the ability to troubleshoot complex testability issues. Experience with RTL design and verification processes.
• Excellent communication and teamwork skills to collaborate with multi-disciplinary teams. Ability to analyze, review, and optimize existing DFT strategies for design and test coverage. Familiarity with semiconductor manufacturing processes and test flows.

Preferred Qualifications :

• Experience with advanced test techniques such as DFT for low-power designs. Familiarity with industry standards such as IEEE 1687 (IJTAG), 1149.1 (JTAG), IEEE 1500 (Core Test), and others.
• Knowledge of Python or other scripting languages for automation.
• Experience with failure analysis, yield improvement and test cost optimization methodologies.
• Experience with SOC (System on Chip) or complex multi-chip designs requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Experienced HireShift 1 (Malaysia)Malaysia, Penang

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

In this position, you will be involved in the training, design and development of next generation System-on-a-Chip which creates great user experience that goes into every Client system.

Within the team, you will be at the forefront of performing SoC Front End related activities ranging from IP integration to SOC verification using state of the art tools and methodology.

As SoC GT, a typical cool day comprises of any of the following:-

• Learning of IP interoperability (in System Verilog, Verilog or other Hardware description language).
• Creative problem solving along the process of integrating an IP into SOC.
• Developing new scenarios to verify the functionally of IP in SOC.
• This includes documenting a test plan, coding test content or coverage points to validate the functionality of new architectural features of next generation designs.
• Developing efficiency capabilities for pre-silicon verification or integration methodology.

Applicant should have:Bachelor/Masters Degree in Electrical and Electronics or Computer System or relevant fields with good CGPAKnowledge of digital design fundamentals and Object Oriented Programming is a plusShift 1 (Malaysia)Malaysia, Penang