דרושים Ai Silicon Mission Control Lead ב-אינטל ב-הודו

Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.
Qualifications:

• Btech/Mtech with 8+ years of experience with complex ASIC/SOC Implementation.
• Solid understanding of system and processor architecture, and the interaction of computer hardware with software.
• Experience designing and implementing complex blocks like CPUs, GPU , and Media blocks and Memory controller.
• Experience with System Verilog/SOC development environment.
• Strong background in scripting - PERL,TCL, Phyton.
• Understanding of Hardware validation techniques
• Knowledge of Industry standard protocols - PCIE, USB, DRR, etc, preferable.
• Experience with Low power/UPFimplementation/verificationtechniques preferable
• Experience with Formal verification techniques is preferable.

Experienced HireShift 1 (India)Virtual India

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Role and responsibilities for this role includes:• Design and develop SW features for AI frameworks - both HW-agnostic and HW-aware, especially in PyTorch device plugin and ML kernel development.
• Enhance and extend the Deep learning training and Inference capabilities in the Software stack.
• Identifying optimization opportunities in the software stack to enhance performance of Deep learning workloads
• Working with Open-source community to support Intel GPUs and upstream code.

Qualifications:

• BTech, MS/MTech & PhD in CS, ECE or related fields with an overall experience of 6 to 12 years.
  Proficient in Advanced C++ (C++ 14/17) and Intermediate skills of Python and GPU programming.
• Experience in developing machine learning kernels such as GEMM, Convolution, Flash attention, MoE etc.
• Hands on experience in one of the frameworks such as PyTorch, Tensorflow or JAX.
• Practical knowledge working on deep learning models such as NLPs & LLMs
• Ability to debug complex issues in multi layered SW systems. Understanding of SW integration in large open-source frameworks.
• Strong understanding of computer architecture and HW-SW optimization techniques.
• Experience in working on frameworks/platforms that have gone to production.
• Effective communication skills and experience with working in a cross-geo teams.Preferable
• Experience in developing and integrating CUTLASS or Triton based kernels
• Knowledge of compiler algorithms for heterogeneous system and Fuser optimizations.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• We are looking for a dynamic and passionate contributors to work on Intel’s next generation GPUs.
• Works with internal engineering teams and stakeholders to deliver optimized complex math kernel operators for Intel GPU's.
• Partners with AI framework and workload engineers as needed to optimize endtoend AI models on Intel hardware features.

Role and responsibilities for this role includes:

• Optimizes performance of AI models through deep knowledge and expertise of AI frameworks, algorithms, models, and related hardware.
• Researches, develops, and adjusts new or existing complex math kernel code to address performance, numeric issues and modify operations to enhance performance with deterministic results.
• Serves as a trusted technical advisor and provides technical enabling.
• Partners with Intel software and hardware product development teams to accelerate and optimize future products in AI.

Qualifications:

• BTech, MS/MTech & PhD in CS, ECE or related fields with an overall experience of 6 to 12 years.
• Proficient in Advanced C++ (C++ 14/17) and Intermediate skills of Python and GPU programming.
• Experience in developing machine learning kernels such as GEMM, Flash attention, MoE, normalization etc.
• Strong understanding of probability theory, linear algebra and statistics.
• Well versed with numerical formats such as float32, float16, flopt8 etc and realted tradeoff's.
• Hands on experience in one of the frameworks such as PyTorch, Tensorflow or JAX.
• Experience in Matlabs Or Cuda.
• Practical knowledge working on deep learning models such as NLPs & LLMs
• Ability to debug complex issues in multi layered SW systems.
• Strong understanding of computer architecture and HW-SW optimization techniques.
• Effective communication skills and experience with working in a cross-geo teams.

• Preferable

  • Experience in developing, optimizing AI or related math kernels, and resolving related numeric issues.

  • Experience in developing, optimizing complex kernels operators like random number generators etc.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Roles and Responsibilities include:

• Design and develop software features for AI frameworks—both hardware-agnostic and hardware-aware.
• Enhance and extend deep learning inference and training capabilities in the software stack.
• Analyze and architect state-of-the-art features across different frameworks and drive development across the full software stack.
• Identify optimization opportunities in the software stack to improve the performance of deep learning workloads.
• Participate in discussions with the open-source community, contribute to development, and upstream software enhancements.

Qualifications:

• B.Tech or M.S./M.Tech in CS, ECE, or related fields with 6–12 years of overall experience.
• Proficient in Python-based complex software implementations; intermediate knowledge of advanced C++ (C++14/17) and parallel programming.
• In-depth, hands-on experience with frameworks such as PyTorch, vLLM, and SGLang.
• Experience with advanced inference-serving features such as disaggregated serving, quantization, speculative decoding, and constrained decoding.
• Strong understanding of LLMs
• Practical knowledge of deep learning models for image and video generation is desirable.
• Ability to debug complex issues in multi-layered software systems; understanding of software integration in large open-source frameworks.
• Strong understanding of computer architecture and HW-SW optimization techniques.
• Effective communication skills and experience working in cross-geo teams.
• Ability to perform performance analysis of code on both host and accelerators/GPUs using open-source and proprietary profilers.
• Understanding of the competitive landscape for technologies in this domain.

Preferred

• Experience developing and integrating CUTLASS or Triton-based kernels for deep learning.
• Knowledge of compiler algorithms for heterogeneous systems and fuser optimizations.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

• Design and develop SW features for AI frameworks - both HW-agnostic and HW-aware, especially in PyTorch device plugin and ML kernel development.
• Enhance and extend the Deep learning training and Inference capabilities in the Software stack.
• Identifying optimization opportunities in the software stack to enhance performance of Deep learning workloads
• Working with Open-source community to support Intel GPUs and upstream code.

Qualifications:

• BTech, MS/MTech & PhD in CS, ECE or related fields with an overall experience of 6 to 12 years.
  Proficient in Advanced C++ (C++ 14/17) and Intermediate skills of Python and GPU programming.
• Experience in developing machine learning kernels such as GEMM, Convolution, Flash attention, MoE etc.
• Hands on experience in one of the frameworks such as PyTorch, Tensorflow or JAX.
• Practical knowledge working on deep learning models such as NLPs & LLMs
• Ability to debug complex issues in multi layered SW systems. Understanding of SW integration in large open-source frameworks.
• Strong understanding of computer architecture and HW-SW optimization techniques.
• Experience in working on frameworks/platforms that have gone to production.
• Effective communication skills and experience with working in a cross-geo teams.Preferable
• Experience in developing and integrating CUTLASS or Triton based kernels
• Knowledge of compiler algorithms for heterogeneous system and Fuser optimizations.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Directs and manages a team of physical design engineers responsible for the physical design implementation of a chip design, subsystem, or block including clocking, timing, and integration. Provides guidance on physical design implementation and analyzes layout designs, power delivery, place, route, clock tree synthesis, and other aspects of physical design. Manages development of complex layout integrated circuit designs, simulation designs, RTL to GDS, logic synthesis, and oversees documentation for SoC development. Reviews circuit layouts architectures and prototypes, ensures issue resolution, and optimizes circuit output. Oversees physical design verification flow at block and chip level and makes recommendations to fix violations for current and future product architecture. Ensures schedule and landing zone requirements of the block, subsystem, or SoC are met. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.Btech/Mtech with 15+ years of experience with complex ASIC/SOC Implementation.Experience in leading team of engineersSolid understanding of system and processor architecture, and the interaction of computer hardware with softwareExperience designing and implementing complex blocks like CPUs, GPU , and Media blocks and Memory controller.Experience with System Verilog/SOC development environment.Strong background in scripting - PERL,TCL, Phyton.Understanding of Hardware validation techniquesKnowledge of Industry standard protocols - PCIE, USB, DRR, etc, preferable.Experience with Low power/UPFtechniques preferableExperience with Formal verification techniques is preferable.Experienced HireShift 1 (India)India, BangaloreThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Directs and manages a team of physical design engineers responsible for the physical design implementation of a chip design, subsystem, or block including clocking, timing, and integration. Provides guidance on physical design implementation and analyzes layout designs, power delivery, place, route, clock tree synthesis, and other aspects of physical design. Manages development of complex layout integrated circuit designs, simulation designs, RTL to GDS, logic synthesis, and oversees documentation for SoC development. Reviews circuit layouts architectures and prototypes, ensures issue resolution, and optimizes circuit output. Oversees physical design verification flow at block and chip level and makes recommendations to fix violations for current and future product architecture. Ensures schedule and landing zone requirements of the block, subsystem, or SoC are met. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.Btech/Mtech with 15+ years of experience with complex ASIC/SOCwith System Verilog/SOC development environment.Strong background in scripting - PERL,TCL, Phyton.Understanding of Hardware validation techniquesKnowledge of Industry standard protocols - PCIE, USB, DRR, etc,with Low power/UPFtechniques preferableExperience with Formal verification techniques is preferable.Experienced HireShift 1 (India)Virtual IndiaThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.