דרושים System Functional Validation Lead ב-אינטל ב-India, Bengaluru

Job Description:

• Responsible for the overall design and Integration of wireless communications connectivity (WiFi, Bluetooth, UWB), cellular, and/or antenna systems and solutions that integrate software, firmware, board, and silicon/SoC components with specific focus on customer requirements and implementation limitations throughout the systems lifecycle.
• May also be responsible for systems architecture and definition, including translating the business opportunity into use cases and developing the product architecture and specifications for required hardware and software needed to deliver system requirements.
• Leads design, analysis, and implementation of component level choices across the integrated wireless systems on performance, features, and cost including analysis of risks and emphasis on ease of use, reliability, security, availability, maintainability, sustainability, and quality.
• Defines systems implementation and integration approach and plans to ensure optimum performance and reliability across hardware and software that comprise the system.
• Delivers endtoend technical solutions to solve customer problems, deploying solutions, executing benchmark tests, and preparing documentation.
• Conducts analysis and makes reliable engineering recommendations to ensurereliability/resiliencyof the wireless infrastructure.
• Monitors and reports on utilization and plans continuous process improvement.
• Makes recommendations to cross functional teams on resolving wireless systems issues including E2E, MAC, PHY, RF and antenna.
• Collaborates with other teams to analyze next generation requirements and opportunities and may influence and guide research and academic collaboration in the space of wireless systems and solutions, including proofofconcept and solutions beyond current industry approaches.

Qualifications:

• BE/M.E/M.Tech. in Electrical Engineering \ Software \ Communications or Computer Science with more than 75 or 8 CGPA in highest degree+5 years of experience intesting/verification/automation.
• Experience in Bluetooth Profile/Stack verification along with PTSDomain expert in Bluetooth/LE core ( HCI and below layers).
• Capable of designing test case from specs and exposure to Automation frameworks.
• Expertise in developing test scripts using Python/PerlExposure in WLAN Coex/OEM/IOP tests with Bluetooth.
• Good in programing languages - C++/C#, Python and scripting languages
• Very good exposure to capturing and performing initial analysis of HCI and Air traces, Ellisys traces.
• Exposure to defect tracking methodologiesFluency in interacting with different teams in a Multisite environment

Experienced HireShift 1 (India)India, Bangalore

Qualifications:

Minimum Qualifications:

• 7+ yrs exp with Bachelor's or master's degree in computer science, Software Engineering, or related technical field.

• Technical Expertise include but not limit to C, C++, Python
• Strong understanding of memory management, pointers, and system-level programming
• Experience with multi-threading, concurrency, and synchronization
• Knowledge of performance optimization techniques
• should be able to Design and implement telemetry collection agents and data processing pipelines
• Develop high-performance, low-latency telemetry systems using C/C++ for system-level components
• Build telemetry analysis tools and automation scripts using Python
• Optimize data collection mechanisms to minimize system overhead and resource consumption
• Implement real-time data streaming and batch processing solutions
• Design APIs and interfaces for telemetry data access and integration
• Debug complex system-level issues across distributed environments
• Ensure telemetry systems meet reliability, scalability, and security requirements
• Collaborate with global platform teams to instrument applications and services
• Maintain and enhance existing telemetry services
• Work effectively in cross-functional teams with product managers, SREs, and other engineers
• Communicate technical concepts clearly to both technical and non-technical stakeholders
• Provide constructive code reviews and technical feedback
• Mentor junior engineers and share knowledge proactively
• Participate actively in design discussions and technical decision-making
Write clean, well-documented, and testable code

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
• Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
• Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.
• Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

• B.Tech. or M.Tech. inElectrical/ElectronicsEngineering with 8-12+ years' of experience.
• Key skills: Experience in all aspects of physical design flow in SOC using Synopsys and cadence tools.
• Experience in timing signoff, formal verification and low power static signoff.
• Experience in all aspects of clock distribution.
• Experience in deep submicron process technology nodes is strongly preferred.
• Solid understanding of power delivery and power plane distributions, power estimation and optimization in SOC.
• Solid understanding industry standard tools for synthesis, place and route and tape out flows.Solid understanding of physical design verification methods to debug LVS/DRC.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology.
• As a DFT engineer direct responsibilities of the role, but not limited to, working on various aspects of PCORE DFT including Spyglass DFT, RTL implementation, Verification, Scan, and ATPG.
• The candidate must be able to drive the DFT implementation for various features incl Scan, MBIST, TAP, etc.
• Previous experience working with manufacturing engineering, pattern delivery, and post-silicon support is a definite plus.

Qualifications:

• Candidate must possess a Master's degree in Electronics or Computer Engineering with at least 7 or more years of experience or a bachelor's degree with at least 9 years of experience in DFT.
• Strong knowledge of ATPG, various fault models, fault grading.
• Knowledge of memory BIST, IJTAG/TAP architecture.
• DFT logic generation, integration, and verification.
• EDA vendor-supported scan architectures and tools, covering synthesis, timing, DRC, ATPG, GLS (Unit delay and Timing/SDF based), and tester bring uppreferably.
• Mentor/Siemens Tessent Shell, TestKompress, ATPG coverage debug.
• Experience in Design Verification (DV) using standard simulators e.g. VCS, Verdi waveform viewer.
• Post Silicon/ATE Bring-Up Support.
• Experience with RTL (Verilog, System Verilog, VHDL)

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• The Client Development Group Bangalore, India is looking for a highly motivated SOC Pre-Si Verification Lead to join the compute die frontend DV team for the next generation of Client SOC.
• ResponsibilitiesOwn or lead verification of complex flows at the SOC, subsystem, or IP levelsLearn about the design and interact with partner teams to define verification strategies and test plans.
• Develop verification environments and run and debug simulations to drive quality.
• Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals.
• Innovate to improve verification efficiency through methodologies or tools Coach and mentor team in your areas of expertise.
• Demonstrate core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity and Inclusion.
• Plan the verification of complex design IP/SS/SoC interacting with the architecture and design engineers to identify verification test scenarios.
• Facilitate interactions with cross functional engineering organizations in supporting Project execution.
• Project planning and scheduling of activities of local team and present and report progress on a regular basis.
• Develop strategies, provide guidance and support team in addressing failure events.Formal : Good to have hands-on experience with formal verification .

Qualifications:

• 7+ years of experience in design verification with a proven track record of delivering complex CPU or SoC IP's/SS.
• Experience with verification for multiple product cycles from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff in SV-UVM.
• Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
• Desirable
• Knowledge in SoC high-speed IO protocols, Fabric-NOC, MemSS, Graphics, Multimedia, Coherency cluster integration and System level flows verification.
• Hands-on experience with formal verification.
• Experience of working on x86 arch based High performing/Low Power SoCs.
• Scripting language such as Python or Perl.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

We are seeking highly motivated, energetic, team-oriented engineer with 4-8 years of relevant experience, willing to take the challenge of delivering IP, Subsystem and SoC Pre-Silicon verification of the latest set of cutting-edge products in Ethernet Product Group in Intel.

In this position, you will participate and lead the verification of IP, Sub-systems and SoC. You will focus on executing pre-Silicon validation plans as per the IP/product release schedule and deliverables, and carry out debug, report failures, report potential failures and help with root-causing the failures. You will be required to create/review verification test plans, drive/participate in discussions across various disciplines to get a clear understanding of requirements, develop the architecture and design of the verification environment in UVM for pre-silicon RTL verification, develops/run/debug tests in System Verilog, mentor's other engineers in using the verification infrastructure and creating test benches. You may work on verification of block/ss/SoC level testing, participate in functional coverage, code coverage reviews and implement feedback. You should also be able to supportpost-silicon/platform

Qualifications:

Minimum Qualifications:B. Tech/M.Tech in Electrical, Electronics/CS streams.

Relevant Experience:3 to 8 Years.

High Proficiency in UVM-ability to architect complex testbenches, verification infrastructure, debugging and issue resolution. AXI, AHB, APB, ACE, AXI Stream protocol knowledge Fundamentals of A-profile Cores, AND/OR Networking Protocols such as PCIe, Ethernet, RDMA, NVME or Experience on Networking flows, AND/OR experience in DDR will be extremely preferred

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Defines, develops, and performs functional validation for integrated SoCs, focusing on validation of IP integration, interaction between IPs, and systemlevel features. Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met. Reviews proposed design changes to assess impact on validation plans, tasks, and timelines. Develops SoC validation methodologies, validation test plans, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis. Performs silicon debug to identify root causes and resolves all functional and triage failures for SoC issues. Tests interactions between various SoC features using validation infrastructure. Develops postsilicon validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing. Publishes SoC validation reports summarizing all validation activities performed, reviews results, and communicates to relevant teams. Works with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for SoC interfaces and to meet desired product specifications. Develops content to create or increase specific IP interactions using a variety of tools and techniques (including patching techniques using microcode, firmware, or custom OS builds). Engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (e.g., simulation, emulation, FPGAs) to ensure silicon readiness.
Qualifications:

• Bachelor's/Master's in Hardware Engineering /Electronics Engineering /Computer Engineering or Computer Science with minimum 6 years to 10 years (Domain Lead position) of related work experience.
• Candidate Must have high degree of Hardware architecture/ microarchitecture experience in CPU/SoC/Chipset/and one of the subsystems areas given below
• Must have [in any one or more domains]
• Deep understanding in one or more protocols from PCIe Express, USB3, DP, Bare metal
• Expertise hands on with programming languages C, C++, Python & Expert understanding Data Structures.
• Good To have Firmware development & validation experience
• Good to have Type C, Thunderbolt [TBT3/ USB4 and USB5] knowledge.
• Excellent written and oral communications and experience working in a cross functional team environment are essential.
• Good Team Player.
• Processes strong problem solving, analytical and debug skills.

Added advantage

• Good working knowledge in C++/Python SW programming for content development and scripting.
• Knowledge of IA/ARM core and system level Power Management architecture who familiar in PMC feature, Gate/Chip level power management transition state & etc.
• Understanding of System Reset related Validation expertise is a plus.
• Solid understanding of the Validation and Debug flows of a complex CPU Silicon
• Knowledge on Validation/ Debug Flows and overall SOC Architecture.
• Pre-silicon Design / Validation knowledge is a value added.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.