דרושים Executive Administrative Assistant - Ai Soc ב-אינטל ב-India, Bengaluru

Job Description:

Role and responsibilities for this role includes:• Design and develop SW features for AI frameworks - both HW-agnostic and HW-aware, especially in PyTorch device plugin and ML kernel development.
• Enhance and extend the Deep learning training and Inference capabilities in the Software stack.
• Identifying optimization opportunities in the software stack to enhance performance of Deep learning workloads
• Working with Open-source community to support Intel GPUs and upstream code.

Qualifications:

• BTech, MS/MTech & PhD in CS, ECE or related fields with an overall experience of 6 to 12 years.
  Proficient in Advanced C++ (C++ 14/17) and Intermediate skills of Python and GPU programming.
• Experience in developing machine learning kernels such as GEMM, Convolution, Flash attention, MoE etc.
• Hands on experience in one of the frameworks such as PyTorch, Tensorflow or JAX.
• Practical knowledge working on deep learning models such as NLPs & LLMs
• Ability to debug complex issues in multi layered SW systems. Understanding of SW integration in large open-source frameworks.
• Strong understanding of computer architecture and HW-SW optimization techniques.
• Experience in working on frameworks/platforms that have gone to production.
• Effective communication skills and experience with working in a cross-geo teams.Preferable
• Experience in developing and integrating CUTLASS or Triton based kernels
• Knowledge of compiler algorithms for heterogeneous system and Fuser optimizations.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• We are looking for a dynamic and passionate contributors to work on Intel’s next generation GPUs.
• Works with internal engineering teams and stakeholders to deliver optimized complex math kernel operators for Intel GPU's.
• Partners with AI framework and workload engineers as needed to optimize endtoend AI models on Intel hardware features.

Role and responsibilities for this role includes:

• Optimizes performance of AI models through deep knowledge and expertise of AI frameworks, algorithms, models, and related hardware.
• Researches, develops, and adjusts new or existing complex math kernel code to address performance, numeric issues and modify operations to enhance performance with deterministic results.
• Serves as a trusted technical advisor and provides technical enabling.
• Partners with Intel software and hardware product development teams to accelerate and optimize future products in AI.

Qualifications:

• BTech, MS/MTech & PhD in CS, ECE or related fields with an overall experience of 6 to 12 years.
• Proficient in Advanced C++ (C++ 14/17) and Intermediate skills of Python and GPU programming.
• Experience in developing machine learning kernels such as GEMM, Flash attention, MoE, normalization etc.
• Strong understanding of probability theory, linear algebra and statistics.
• Well versed with numerical formats such as float32, float16, flopt8 etc and realted tradeoff's.
• Hands on experience in one of the frameworks such as PyTorch, Tensorflow or JAX.
• Experience in Matlabs Or Cuda.
• Practical knowledge working on deep learning models such as NLPs & LLMs
• Ability to debug complex issues in multi layered SW systems.
• Strong understanding of computer architecture and HW-SW optimization techniques.
• Effective communication skills and experience with working in a cross-geo teams.

• Preferable

  • Experience in developing, optimizing AI or related math kernels, and resolving related numeric issues.

  • Experience in developing, optimizing complex kernels operators like random number generators etc.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Roles and Responsibilities include:

• Design and develop software features for AI frameworks—both hardware-agnostic and hardware-aware.
• Enhance and extend deep learning inference and training capabilities in the software stack.
• Analyze and architect state-of-the-art features across different frameworks and drive development across the full software stack.
• Identify optimization opportunities in the software stack to improve the performance of deep learning workloads.
• Participate in discussions with the open-source community, contribute to development, and upstream software enhancements.

Qualifications:

• B.Tech or M.S./M.Tech in CS, ECE, or related fields with 6–12 years of overall experience.
• Proficient in Python-based complex software implementations; intermediate knowledge of advanced C++ (C++14/17) and parallel programming.
• In-depth, hands-on experience with frameworks such as PyTorch, vLLM, and SGLang.
• Experience with advanced inference-serving features such as disaggregated serving, quantization, speculative decoding, and constrained decoding.
• Strong understanding of LLMs
• Practical knowledge of deep learning models for image and video generation is desirable.
• Ability to debug complex issues in multi-layered software systems; understanding of software integration in large open-source frameworks.
• Strong understanding of computer architecture and HW-SW optimization techniques.
• Effective communication skills and experience working in cross-geo teams.
• Ability to perform performance analysis of code on both host and accelerators/GPUs using open-source and proprietary profilers.
• Understanding of the competitive landscape for technologies in this domain.

Preferred

• Experience developing and integrating CUTLASS or Triton-based kernels for deep learning.
• Knowledge of compiler algorithms for heterogeneous systems and fuser optimizations.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

• Design and develop SW features for AI frameworks - both HW-agnostic and HW-aware, especially in PyTorch device plugin and ML kernel development.
• Enhance and extend the Deep learning training and Inference capabilities in the Software stack.
• Identifying optimization opportunities in the software stack to enhance performance of Deep learning workloads
• Working with Open-source community to support Intel GPUs and upstream code.

Qualifications:

• BTech, MS/MTech & PhD in CS, ECE or related fields with an overall experience of 6 to 12 years.
  Proficient in Advanced C++ (C++ 14/17) and Intermediate skills of Python and GPU programming.
• Experience in developing machine learning kernels such as GEMM, Convolution, Flash attention, MoE etc.
• Hands on experience in one of the frameworks such as PyTorch, Tensorflow or JAX.
• Practical knowledge working on deep learning models such as NLPs & LLMs
• Ability to debug complex issues in multi layered SW systems. Understanding of SW integration in large open-source frameworks.
• Strong understanding of computer architecture and HW-SW optimization techniques.
• Experience in working on frameworks/platforms that have gone to production.
• Effective communication skills and experience with working in a cross-geo teams.Preferable
• Experience in developing and integrating CUTLASS or Triton based kernels
• Knowledge of compiler algorithms for heterogeneous system and Fuser optimizations.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

General Expectation:

• Designs, develops, integrates, tests, validates, and/or debugs software to enable Intel product features to enable or utilize Artificial Intelligence, including machine learning, deep learning, and GenAI.

• Understands internal and external partner software and develops software across the stack (spanning firmware, drivers, OS, middleware, frameworks, algorithms, and applications) as required to enable and optimize specific AI features, capabilities, solutions, reference platforms, or Intel products.

• Includes the development of reference AI software and improving or enabling customer designs to obtain the greatest value of Intel AI products, the development and/or optimization of workloads for AI benchmarks, and workloads for simulation to support preSi power and performance analysis and architecture

Qualifications:

• Masters in Computer Science/Engineering, Electronic Engineering, or Electrical Engineering. Experience - 7+ Years.

• Development experience in Linux environment (multiple distributions like deb, RPM etc.) and developing open-source SW including upstream experience. SDL knowhow is an added plus.

• Proficiency in Python and C++ programming.

• Experience of at least 8 years in SW development.

• Excellent written and verbal communication skills

• Relevant experience in AI domain with GenAI, Models, training, inference, AI frameworks etc.

Experienced HireShift 1 (India)India, Bangalore

Job Description:

• Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
• Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
• Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.
• Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

• B.Tech. or M.Tech. inElectrical/ElectronicsEngineering with 8-12+ years' of experience.
• Key skills: Experience in all aspects of physical design flow in SOC using Synopsys and cadence tools.
• Experience in timing signoff, formal verification and low power static signoff.
• Experience in all aspects of clock distribution.
• Experience in deep submicron process technology nodes is strongly preferred.
• Solid understanding of power delivery and power plane distributions, power estimation and optimization in SOC.
• Solid understanding industry standard tools for synthesis, place and route and tape out flows.Solid understanding of physical design verification methods to debug LVS/DRC.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience.Related technical experience should be in/with: Silicon Design and/orPreferred Qualifications:Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies.The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.Experience in Xeon CPU Pre-Silicon or Post Silicon Validation.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orExperienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.