דרושים Fpga Sw Validation Engineer ב-Arm ב-United Kingdom, Cambridge

By joining the team, you will interact closely with world-wide CPU RTL designers and implementation teams to investigate and evaluate new micro-architectural ideas and design trade-offs that will make the micro-architecture for the next products successful for the target sectors. You will evaluate these ideas and analyse CPU performance and power developing and using C++ based models of the micro-architecture. You will also coach and mentor more junior engineers to help them grow and become deep experts on the field.

The key objectives of this role include:

• Help driving the technical direction of the team, which develops, tests and maintains software models of Arm's advance CPUs.
• Engage with hardware design engineers to prune the design space of next generation products, understanding power and performance opportunities on current processors and investigate potential micro-architectural improvements.
• Support the mentorship and coaching of other specialists; sharing your technical expertise and experience.
• With your help, we will keep improving the effectiveness of Arm modelling methodologies.
• Our team collaborates with performance, design and implementation engineers across the world. You would be involved on the communication and alignment of activities related to integration, methodologies, strategies, etc.

• Good interpersonal skills and capacity to work efficiently with local and remote teams.
• Detailed understanding of CPU micro-architecture.
• Experience of performance modelling.
• Experience of exploring and evaluating ideas and performance related to processor micro-architecture.
• Proven experience in C++.

• Team leadership, including planning and managing tasks, as well as delivery to specification and schedule.
• Strong software development experience, including design specification, coding, testing, and debugging.
• Experience with RTL and SystemC simulators.
• Experience with power models.
• Familiarity with Arm architectures and instruction sets.
• Knowledge of System Architecture and System Software including OS kernel internals.
• Experience of Unix development environment.
• University degree, ideally in electronic engineering or computer science, although other graduates would be considered if they have meaningful experience.

You will get to utilise your engineering skills to build support for technologies and influence millions of devices for years to come. You’ll share ideas with and learn new skills from some of the best engineers in the world!

• Being a member of the core arm64 Linux Kernel team responsible for maintaining the upstream Linux port and user space tools
• Review code on public mailing list and upstream code to various Linux subsystems including perf
• Actively work on improving performance and security of upstream Linux Kernel on modern arm64 hardware
• Support our kernel maintainers by helping reduce technical debt and review burden of various subsystems
• Do investigations of new architecture features and how they can used by Linux
• Upstream support for new architecture features

• Proficient C programmer
• Desire and ability to work as part of a team and the Linux community
• Strong understanding of operating system fundamentals
• Credible experience of developing sophisticated low level software

• Armv8-A Architecture
• Arm64 assembly language
• Proficient in Linux Memory Management and Virtualisation
• Credible experience of working in the Linux upstream

• Implement verification strategies to ensure detailed testing of the assigned Subsystem or SoC module.
• Work closely with design engineers, architects, and other verification engineers to understand design requirements and plan verification.
• Apply excellent verbal and written communication skills to report verification progress, issues, and results to customers.
• Automate test cases and regression suites to improve verification efficiency and coverage.

Required Skills and Experience :

• Solid understanding of SoC Verification (using C Testcases), hardware description and verification languages e.g. SystemVerilog, Verilog, VHDL.
• Understanding of Computer architecture, bus protocols (e.g., AXI, AHB), and peripherals.
• Experience with Tcl, Python or other scripting languages.

• Experience with ARM-based designs and/or ARM System Architectures.
• Familiarity with ARM debugger and trace features e.g ARM DS, DSTREAM.
• Knowledge of memory subsystems and/or high speed peripherals (e.g. PCIe/CXL) will be a plus, including integration of these IP models into a design.

Develop in depth understanding of ML workload, develop algorithms and optimization techniques to drive PPA (Performance, Power, Area) on current and future Arm platforms.

1. Implementation of performance critical machines specific kernel or ARM assembly code on dedicated hardware accelerator and CPU to drive algorithm and architecture exploration
2. Collaborate with ML Algorithm development team to explore performance critical analysis
3. Develop internal tooling capabilities to support algorithmic and architecture exploration

• Develop performance critical assembly code to accelerate ML operations done in low precision arithmetic
• Develop performance critical kernel to accelerate fusing of multiple ML operations on accelerators
• Explore different quantization schemes and assess performance PPA trade off

• 3+ years experience in developing performance critical kernel on dedicated accelerator, GPU or CPU
• Graduate students in Computer Engineering, Electrical Engineering, Computer Science or other related technical fields
• Deep knowledge in machine learning, deep learning, and neural network design, optimization, and compression techniques
• Overall high-level knowledge of computer architecture, systems, and HW-SW co-design
• Ability to develop and work with large software systems in programming languages like Python
• Knowledge of cutting-edge deep learning libraries such as Tensorflow, and Pytorch
• Willing to learn and train large deep learning models on GPU-based systems

• Experience with ML model design, optimization, and HW-SW co-development methodology
• ML Model Optimization techniques targeting PPA (Performance, Power, and Area) of neural networks on ARM compute platforms
• Adaptability to the fast-moving ML industry and willingness to learn new technology in a very dynamic environment

Working on interesting new projects with leaders in the field is exciting, but we also know how important it is to receive support. That's why throughout your internship, you can expect regular feedback and development opportunities, social activities to connect with your peers, an end of internship celebration, plus the opportunity to be *considered for future Graduate positions (*subject to performance). #getreadytogrow

In addition to a competitive salary and rewards package, our on-the-job learning and mentoring/buddy schemes provide unparalleled learning and networking opportunities from the best in the industry.

Verification engineers in the GPU Group are responsible for innovation and development of next-generation GPU IP for graphics and compute.

Required Skills and Experience

• Strong hands-on experience in System Verilog and UVM methodology OR formal verification
• Exposure to all stages of unit verification: collection of requirements, defining test methodologies, writing test plans, developing testbenches and test cases, debugging complex designs and testbenches, coverage closure.
• Excellent communication skills and ability to work in a large team.

• Experience with both UVM & formal verification
• Experience working with project management and leads on planning tasks, setting schedules, and quality checkpoints.
• Experience mentoring team members or reviewing other’s technical work.
• Knowledge of scripting (e.g. Python, Perl or Unix shell scripting).
• Experience with continuous integration platforms (e.g., Jenkins) and version control systems (e.g., Git).
• Experience with verification for Safety and Security requirements.
• Understanding of the fundamentals of computer architecture.

The role of Performance Engineer requires to:

• Utilise pre-silicon platforms for next-gen systems to gain insights into new use cases
• Ensure that IP and system around it delivers powerful AI performance
• Engage with specialists across Arm to understand, explore and challenge the limits of performance capabilities
• Help to influence direction of AI software and IP

• Software development, with very good programming skills, preferably C++ and Python
• Ability to quickly investigate and debug large software frameworks
• A real passion for data analysis
• Curiosity to make positive impact, both in our team, and in the wider Arm ecosystem
• Very good interpersonal, collaboration and communication skills
• A degree, or higher in computational or numerate subject, or experience in a related field

In this role you will focus on analysing and enabling optimal performance and power efficiency for advanced machine learning and compute workloads on next-generation Arm IPs and systems, including emerging architectural features such as the Scalable Matrix Extension (SME). You'll work with pioneering pre-silicon platforms: software models, RTL simulation, emulation, and FPGA environments. These platforms are critical for assessing and validating these next-generation designs. Another core aspect of the role is work on evaluating and tuning neural network execution across frameworks like LiteRT, ONNX Runtime, and the Arm Compute Library (ACL) to fully exploit the capabilities of brand-new Arm hardware to achieve the best performance to power ratio. You will also work on low-level system software and develop advanced debugging skills in a pre-silicon context.

As a Security Engineer – Fuzzing Specialist, you will own and evolve our coverage-guided fuzzing program. Your mission is to uncover hard-to-reach security flaws before attackers do, drive fixes to closure, and help product teams to embrace dynamic testing like fuzzing. You’ll scout for new attack surfaces, craft high-performance fuzzing harnesses, and design custom sanitisers that push the state of the art. Success means measurable coverage gains, actionable crash reports, and products that ship with provable resilience.

• Map & prioritise fuzzing surfaces across services, libraries, APIs, and protocols; maintain a living risk-based roadmap.
• Design, build, and extend fuzzing harnesses (libFuzzer, AFL++, Honggfuzz, etc.) that improve code-path exploration and minimise false positives.
• Continuously improve coverage by growing seed corpus, deploying targeted mutation strategies, and integrating new instrumentation techniques.
• Automate crash triage & root-cause analysis; distinguish exploitable vulnerabilities from benign faults and drive CVE-level findings to remediation.
• Develop custom sanitisers to expose classes of bugs traditional fuzzing misses.
• Validate fixes & guard against regressions through differential fuzzing and regression corpora.
• Assess external disclosures (bug bounties, supply-chain advisories) to determine fuzzing detectability and refine harnesses when gaps are found.
• Document, report, and share insights — from coverage metrics to post-mortems to create data-driven security.

• 1+ years in application or product security with a deep focus on coverage-guided fuzzing.
• Hands-on expertise with at least one modern fuzzing framework (e.g., libFuzzer, AFL++, Honggfuzz).
• Proficient in C/C++ plus strong scripting ability in Python for automation.
• Solid understanding of memory-safety vulnerabilities, undefined behaviour, sanitisers, and compiler instrumentation.
• Demonstrated ability to triage crashes using debuggers, profilers, and reverse-engineering tools (gdb/lldb, IDA/Ghidra).
• Excellent written communication for documenting findings and influencing engineering teams.

• Contributions to open-source fuzzing tools, sanitisers, or security research publications.
• Knowledge of distributed fuzzing at scale (GCP/AWS, Kubernetes, or bare-metal clusters).
• Familiarity with kernel, embedded, or firmware fuzzing (e.g., Syzkaller, QEMU-based harnesses).
• Background in reverse engineering, static analysis or symbolic execution.
• Experience integrating fuzzing into CI/CD pipelines and tracking coverage metrics.