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דרושים Mixed Signal Circuit Design Engineer ב-אפל ב-Australia, Melbourne
מצאו את ההתאמה המושלמת עבורכם עם אקספוינט! חפשו הזדמנויות עבודה בתור Mixed Signal Circuit Design Engineer ב-Australia, Melbourne והצטרפו לרשת החברות המובילות בתעשיית ההייטק, כמו Apple. הירשמו עכשיו ומצאו את עבודת החלומות שלך עם אקספוינט!
חברה (1)
אופי המשרה
קטגוריות תפקיד
שם תפקיד (1)
Australia
Melbourne
נמצאו 11 משרות
26.08.2025
A
Apple SerDes Circuit Design Engineer Australia, Victoria, Melbourne
תיאור:
You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus, you will get an opportunity to work on designs which makes the best systems. This enables you to learn to end-to-end system while exceeding the highest expectations of quality, innovation and efficiency.If you have strong fundamentals and a track record of tackling technical challenges, If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and solve problems,
We work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best in class power, performance, and area (PPA).
- BSEE with 3+ years of proven experience.
- The ideal candidate should have deep understanding of AMS design with experience in high-speed serial links.
- Solid understanding of designing AMS circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters
- Understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
- Deep understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops)
- Proven experience working on system and architecture teams to drive block-level and IP requirements
- Proven track record working with large teams and guiding junior engineers
- Experience with high speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with solid understanding of digital design concepts
- Experience and proven understanding of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 20+ Gbps NRZ and PAM applications
- Experience with EQ adaptation methods and circuit interactions to improve PPA
- Solid understanding of CDR architectures and implementations
- Experience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS)
- Hands-on experience to drive lab testing, debug and data analysis
- Hands-on experience in advanced CMOS technologies, design with FinFet technology
- Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
- EXPERIENCE IN THE FOLLOWING AREAS IS A PLUS
- Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime)
- Concepts of IP delivery and quality checks
- Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is helpful
- Skills in scripting and automation to improve efficiency are highly desirable
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משרות נוספות שיכולות לעניין אותך
25.08.2025
A
Apple Design Verification Engineer Australia, Victoria, Melbourne
תיאור:
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.
- BS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent
- Working knowledge of OOP, SystemVerilog and UVM
- Working knowledge in developing scalable and portable test-benches
- Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations
- Experience with power-aware (UPF) or similar verification methodology
- Knowledge of one of the scripting languages such as Python, Perl, TCL
- Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
- Knowledge of formal verification methodology is a plus but not required
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25.08.2025
A
Apple Analog Mixed Signal IC Designer Australia, Victoria, Melbourne
תיאור:
You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus, you will get an opportunity to work on designs which makes the best systems. This enables you to learn to end-to-end system while exceeding the highest expectations of quality, innovation and efficiency.If you have strong fundamentals and a track record of tackling technical challenges, If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and solve problems,
We work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best in class power, performance, and area (PPA).
- BSEE required
- Technical Expertise: Demonstrated proficiency in high-speed analog/mixed-signal architecture and circuit design, including frequency synthesizers, ADCs, DACs, RO/LC oscillators, regulators, on-chip sensors, compensation techniques, droop detection and recovery, and digitally-assisted analog techniques.
- Clocking Mastery: Deep understanding of clocking fundamentals, with a solid grasp of phase noise, jitter analysis, budgeting, and feedback loop dynamics.
- Simulation and Modeling: Skilled in designing/debugging RTL, developing System Verilog models, and performing behavioral simulations to explore new architectural performance and functions.
- Attention to Detail: Exceptional focus on understanding the problems at hand and their systemic impacts, ensuring thoroughness in problem-solving
- EXPERIENCE IN THE FOLLOWING AREAS IS A PLUS
- Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime)
- Concepts of IP delivery and quality checks
- Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is helpful
- Skills in scripting and automation to improve efficiency are highly desirable
- Team Collaboration: Outstanding teamwork capabilities paired with strong productivity and scripting skills, ideally with experience in using industry-standard design tools.
Expand
12.05.2025
A
Apple Analog Mixed Signal IC Designer Australia, Victoria, Melbourne
תיאור:
You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus, you will get an opportunity to work on designs which makes the best systems. This enables you to learn to end-to-end system while exceeding the highest expectations of quality, innovation and efficiency.If you have strong fundamentals and a track record of tackling technical challenges, If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and solve problems,
We work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best in class power, performance, and area (PPA).
- BSEE required
- Technical Expertise: Demonstrated proficiency in high-speed analog/mixed-signal architecture and circuit design, including frequency synthesizers, ADCs, DACs, RO/LC oscillators, regulators, on-chip sensors, compensation techniques, droop detection and recovery, and digitally-assisted analog techniques.
- Clocking Mastery: Deep understanding of clocking fundamentals, with a solid grasp of phase noise, jitter analysis, budgeting, and feedback loop dynamics.
- Simulation and Modeling: Skilled in designing/debugging RTL, developing System Verilog models, and performing behavioral simulations to explore new architectural performance and functions.
- Attention to Detail: Exceptional focus on understanding the problems at hand and their systemic impacts, ensuring thoroughness in problem-solving
- EXPERIENCE IN THE FOLLOWING AREAS IS A PLUS
- Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime)
- Concepts of IP delivery and quality checks
- Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is helpful
- Skills in scripting and automation to improve efficiency are highly desirable
- Team Collaboration: Outstanding teamwork capabilities paired with strong productivity and scripting skills, ideally with experience in using industry-standard design tools.
Expand
11.05.2025
A
Apple Layout Engineer Australia, Victoria, Melbourne
תיאור:
Layout Engineers are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop world-leading SOCs. As a part of the AMS layout team, you will be delivering fully-verified, layout. This includes the following: Crafting sophisticated layout for mixed signal and analog circuits in deep sub-micron CMOS technologies. Reviewing and analyzing floorplans and intricate circuits. Running complete sets of design verification tools available on AMS blocks. Working with circuit design engineers plan/schedule work and coordinate vital layout tradeoffs as needed. Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. Exceeding engineering specifications and expectations by working closely with the circuit design team. Applying sophisticated CAD tools and mask design knowledge to deliver accurate and robust layout that matches performance, area and power requirements.
- B.S. EE & CS or equivalent plus 3 years of proven experience or equivalent.
- Excellent communication skills and able to work with multi-functional teams
- Familiar with CAD tools like Virtuoso, Innovus, Calibre is a plus
- Programming knowledge in SKILL, Perl, and/or Python is a bonus
- Concentration in Mixed-Signal and RF Integrated Circuits is helpful
Expand
21.04.2025
A
Apple SerDes Circuit Design Engineer Australia, Victoria, Melbourne
תיאור:
You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus, you will get an opportunity to work on designs which makes the best systems. This enables you to learn to end-to-end system while exceeding the highest expectations of quality, innovation and efficiency.If you have strong fundamentals and a track record of tackling technical challenges, If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and solve problems,
We work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best in class power, performance, and area (PPA).
- BSEE with 3+ years of proven experience.
- The ideal candidate should have deep understanding of AMS design with experience in high-speed serial links.
- Solid understanding of designing AMS circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters
- Understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
- Deep understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops)
- Proven experience working on system and architecture teams to drive block-level and IP requirements
- Proven track record working with large teams and guiding junior engineers
- Experience with high speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with solid understanding of digital design concepts
- Experience and proven understanding of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 20+ Gbps NRZ and PAM applications
- Experience with EQ adaptation methods and circuit interactions to improve PPA
- Solid understanding of CDR architectures and implementations
- Experience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS)
- Hands-on experience to drive lab testing, debug and data analysis
- Hands-on experience in advanced CMOS technologies, design with FinFet technology
- Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
- EXPERIENCE IN THE FOLLOWING AREAS IS A PLUS
- Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime)
- Concepts of IP delivery and quality checks
- Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is helpful
- Skills in scripting and automation to improve efficiency are highly desirable
Expand
20.04.2025
A
Apple RTL Design Engineer Australia, Victoria, Melbourne
תיאור:
In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits with embedded micro-controller, advanced DFT architectures and very low power design requirements. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing RTL assertions, debugging code, and otherwise interacting with the design verification team. Additionally, you will be responsible for various front end methodology flows that include pre-silicon power analysis, clock domain crossing, reset domain crossing and unified power flow UPF). You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
- BS degree in technical discipline with minimum 10 years of relevant experience.
- Deep knowledge of mixed signal concepts
- Deep knowledge of RTL design fundamentals (control and data path).
- Deep knowledge of Verilog and SystemVerilog.
- Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers, reset domain crossing, unified power flow, logic equivalence checkers).
- Working knowledge of synthesis, static timing, and DFT (scan, analog/digital functional/production test).
- Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques.
- Deep knowledge of scripting languages. Perl and Python are plusses.
- Deep knowledge of Algorithm developments.
- Strong communication and presentation skills.
- SERDES architecture knowledge is a plus.
Expand
תיאור:
You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus, you will get an opportunity to work on designs which makes the best systems. This enables you to learn to end-to-end system while exceeding the highest expectations of quality, innovation and efficiency.If you have strong fundamentals and a track record of tackling technical challenges, If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and solve problems,
We work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best in class power, performance, and area (PPA).
- BSEE with 3+ years of proven experience.
- The ideal candidate should have deep understanding of AMS design with experience in high-speed serial links.
- Solid understanding of designing AMS circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters
- Understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
- Deep understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops)
- Proven experience working on system and architecture teams to drive block-level and IP requirements
- Proven track record working with large teams and guiding junior engineers
- Experience with high speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with solid understanding of digital design concepts
- Experience and proven understanding of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 20+ Gbps NRZ and PAM applications
- Experience with EQ adaptation methods and circuit interactions to improve PPA
- Solid understanding of CDR architectures and implementations
- Experience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS)
- Hands-on experience to drive lab testing, debug and data analysis
- Hands-on experience in advanced CMOS technologies, design with FinFet technology
- Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
- EXPERIENCE IN THE FOLLOWING AREAS IS A PLUS
- Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime)
- Concepts of IP delivery and quality checks
- Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is helpful
- Skills in scripting and automation to improve efficiency are highly desirable
Expand
משרות נוספות שיכולות לעניין אותך
בואו למצוא את עבודת החלומות שלכם בהייטק עם אקספוינט. באמצעות הפלטפורמה שלנו תוכל לחפש בקלות הזדמנויות Mixed Signal Circuit Design Engineer בחברת Apple ב-Australia, Melbourne. בין אם אתם מחפשים אתגר חדש ובין אם אתם רוצים לעבוד עם ארגון ספציפי בתפקיד מסוים, Expoint מקלה על מציאת התאמת העבודה המושלמת עבורכם. התחברו לחברות מובילות באזור שלכם עוד היום וקדמו את קריירת ההייטק שלכם! הירשמו היום ועשו את הצעד הבא במסע הקריירה שלכם בעזרת אקספוינט.