דרושים Senior Board Design Lead ב-אינטל ב-Israel, Petah Tikva

Job Description:

You will be exposed to High-Speed I/O protocols such as PCIe, DDR5, and PAM4 Ethernet, which are a part of our Ethernet Infrastructure Processing Unit (Intel IPU) and Foundation NIC (FNIC) Ethernet product lines.

In this position:

• You will lead a team of developers and also work hands-on to design and develop digital and analog circuit boards for HW-Engineering products.
• Develop board design from schematic through Silicon power-on debug and may interface with other board design and test module development teams to drive innovation initiatives.
• Identifying new hardware solutions, providing technical leadership to working groups/task forces to resolve hardware, schematics, layout, DFx issues through debugging and reviews, and part/component selection management.
• learning the specification of each interface and the required design limitations that should be verified.
• requires high-frequency signal and power integrity and a good understanding of RF circuits and electromagnetic wave propagation.

Qualifications:

• B.Sc./M.Sc. Electrical Engineer with over 10 years of relevant experience in hardware/board design.
• 4+ years as a team lead, including planning and design-flows buildup.
• Experience with PCB technology and layout (Analog and Digital) including stack-up, placement, routing, and SI/PI.
• Lab work experience in high accuracy signals measurement.
• Excellent debugging skills, ability to analyze problems, diagnose the root cause and apply corrective action.
• Familiar with layout technics.
• FPGA and Verilog coding skills.
• Test measurement instrument hands-on operation.
• Programming knowledge and experience.
• Strong verbal and written communication skills in English.
• Comprehensive understanding of system architecture.

Experienced HireShift 1 (Israel)Israel, Petah-Tikva

Qualifications:

• BSc/MSc in electrical or computer engineering.
• 10+ years of hands-on experience in VLSI physical design, with a proven track record of successful projects working with advanced technology nodes.
• Excellent familiarity with all Physical Design implementation flows and techniques, including floorplanning, placement, routing, and timing closure.
• Proficiency in Synopsys EDA tools (Cadence is an advantage).
• Knowledge of scripting languages such as Python, Perl, or TCL.
• Strong understanding of STA, IR drop, EM analysis, DRC/LVS, and ECO flows. Experience with power, performance, and area (PPA) optimization.
• Experience in managing and mentoring technical teams.
• Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills

Experienced HireShift 1 (Israel)Israel, Petah-Tikva

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:
Qualifications:Experienced HireShift 1 (Israel)Israel, Petah-TikvaIsrael, Haifa

Lead the design and development of high-speed SERDES and advanced power management circuits (e.g., DC-DC, LDOs converters, switched-capacitor regulators, etc...).Define architecture and specifications for analog/mixed-signal IPs.Oversee schematic design, simulation, layout supervision, and post-layout verification.Collaborate with digital, layout, and verification teams to ensure first-pass silicon success.Drive design reviews, documentation, and design sign-off processes.Mentor and guide junior engineers, fostering a culture of technical excellence and innovation.Interface with other teams and internal stakeholders (System, Post Silicon validation, production and reliability) to align design goals with product requirements.BSc./M.Sc. in Electrical Engineering8+ years of experience in analog/mixed-signal IC design, with at least 2 years in a leadership role.Proven track record in designing and delivering SERDES and power management IPs in advanced CMOS nodes (e.g., 7nm, 5nm).Strong understanding of signal integrity, power integrity, and layout-aware design.Proficiency in EDA tools (Cadence Virtuoso, Spectre, EMIR tools, etc.).Excellent communication, leadership, and project management skills.Experienced HireShift 1 (Israel)Israel, Petah-Tikva

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

As part of this role, you will lead the full development cycles of design units from architecture to tape-out and work in full collaboration with the architecture, validation, Backend, Firmware, Software, and SOC teams.

Qualifications:

• BSc. in Electrical Engineering or BSc. in Computer Engineering.
• Minimum 5 years of experience in chip design.
• Experience with System Verilog or Verilog.
• Excellent problem-solving ability.
• Good communication skills, Team player, High work motivation.

Advantages:

• Experience with Networking designs.
• Tools experience: LINT/CDC/RDC/SDC.
• Basic knowledge with Synthesis tools.
• Scripting skills in Perl/Python.

Experienced HireShift 1 (Israel)Israel, Petah-TikvaIsrael, Haifa

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

B.Sc./M.Sc. in Electrical Engineering or related field.10+ years of experience in physical design, with at least 2 years in a technical leadership role.Proven track record of successful tapeouts in advanced FinFET nodes.Deep understanding of physical design flows, timing analysis, power integrity, and physical verification.Hands-on experience with industry-standard EDA tools (e.g., Fusion Compiler, PrimeTime, RedHawk-SC, Calibre (Innovus is an advantage).Strong analytical, organizational, and communication skills.Experienced HireShift 1 (Israel)Israel, Petah-Tikva

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.
Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:

• BSc or Msc in Electrical Engineering or Computer Engineering
• At least 6 years of relevant experience in ASIC chip design with familiarity with the entire development flow from definition to Tape-Out
• Good problem solving ability
• Excellent team work and communication skills
• Experience with Networking design

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Experienced HireShift 1 (Israel)Israel, Petah-Tikva