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Apple Design Verification Engineer Czechia, Prague, Prague 528708052
30.03.2024
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Key Qualifications
- Deep knowledge of SystemVerilog test-bench language and UVM Experience developing scalable and portable test-benches.
- Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations.
- Experience with serial protocols such as PCIe or USB Experience with mixed signal verification methodology for IPs such as PHYs, PLLs etc.
- In lieu of UVM knowledge, C/C++ level knowledge.
- Deep knowledge of one of the scripting languages: Python, Perl, TCL.
- Deep knowledge of formal verification methodology.
Description
In this role, you will be responsible for ensuring a bug-free first silicon for part of the SoC / IP and are encouraged to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification plans for all features under your care. Implement verification plans, including design bring-up, Design Verification environment bring-up, regression enabling for all features under your care, de-bug of the test failures. Develop block, IP and SoC level test-benches Track and report Design Verification progress using a variety of metrics, including bugs and coverage.
Education & Experience
BS degree in technical discipline with minimum 10 years of relevant experience.
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