Bachelor's degree in Electrical Engineering, Semiconductor Processing, or a related field, or equivalent practical experience.
4 years of experience in VLSI technologies, product and test engineering, and semiconductor processing.
Experience with Yield and Fail Pareto Analysis using JMP, Exensio, Datapower or O+.
Experience in Integrated Circuit (IC) qualification, data review, production release, System Level Testing, test time reduction and yield improvement.
Preferred qualifications:
8 years of experience in VLSI technologies, Product and Test Engineering, Semiconductor processing.
Experience in Test and Design for test (DFT) techniques, and with structural tests such as Scan/ATPG, JTAG, Memory BIST and sensors such as PVT/temperature/current/droop sensors, etc.
Experience with advanced packaging such as 2.5d, 3d, InFo, or Automatic Test Equipment (ATE) test platforms such as Advantest 93K , Teradyne UltraFlex SOC test system.
Experience with test chip design, development and testing methodologies.
Knowledge of reliability stress, device qualification and associated processes.