Nvidia Signoff Methodology Engineer - New College Grad 

United States, California 

88243556

What You'll Be Doing:

• Improve and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for high-speed designs, with focus on CAD and automation.

• Develop custom flows for validating QoR of ETM models, both of std cells and custom IPs.

• Developflows/recommendations

• Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance.

• Develop tools, and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer.

• Work on various aspects of STA, constraints, timing and power optimization.

What We Need To See:

• MS or PhD in Electrical or Computer Engineering (or equivalent experience).

• Good understanding of modeling circuits for sign-off.

• Knowledge of extraction, device physics, STA methodology and EDA tools limitations.

• Shown understanding of mathematics/physics fundamentals of electrical design.

• Understanding of 3DIC, stacking, packing, self-heating and its impact on timing/STA closure.

• Background with crosstalk, electro-migration, noise, OCV, timing margins.

• Familiarity with Clocking specs: jitter, IR drop, crosstalk, spice analysis.

Ways to Stand out from the Crowd:

• Shown interpersonal skills across multiple teams is a plus.