We are seeking a highly skilled and experienced engineer to develop and enhance Design for Testability (DFT) flows and methodologies. The ideal candidate will play a key role in advancing the CAD toolchain within the Design Enablement Group, ensuring efficient and effective DFT practices for complex SoC designs. This role requires in-depth knowledge of DFT concepts, test architecture, and flow automation, and hands-on experience in building and maintaining robust DFT flows.
Key Responsibilities:
- Develop, enhance, and maintain DFT flows and methodologies to optimize testability and fault coverage in semiconductor devices.
- Collaborate with cross-functional teams (Design, Verification, Test Engineering, CAD) to define and implement efficient DFT strategies and workflows.
- Integrate various test strategies such as scan insertion, Built-In Self-Test (BIST), Memory BIST (MBIST), Boundary Scan, and JTAG into the design flow.
- Automate and customize DFT CAD flows using scripting languages (Tcl, Python, Perl) to improve productivity and reduce design cycle times.
- Drive continuous improvements in the DFT flow to support evolving design complexities, process nodes, and packaging technologies.
- Ensure the scalability of DFT methodologies for multi-million gate SoCs, advanced packaging solutions, and chiplets (system of chips).
- Provide technical leadership and mentorship to junior engineers and collaborate with EDA tool vendors for tool improvements.
- Develop and maintain DFT documentation, design guidelines, and best practices for various design teams.
- Analyze test coverage data, debug test failures, and ensure compliance with industry standards and design specifications.
- Collaborate in tape-out readiness reviews and support silicon bring-up and failure analysis post-silicon.