Ai Frameworks Architect jobs at Intel

Job Description:

Since pioneering the world’s first hybrid silicon laser, IPS has led the industry in scalable, high-volumemanufacturing andadvanced photonics development. Our mission: deliver next-generation bandwidth growth with smaller form factors, co-packaging, and speeds from 400G today to 1.6T+ tomorrow.

We are seeking a Lead Analog SerDes Architect / Design Engineer to join our team and shape the future of data center connectivity. In this role, you will:

• Defining circuit architecture and enabling designs meeting power, and performance for next generation optical interconnects based on system specifications.
• As part of the team developing key integrated circuit components the engineer must be able to work collaboratively leading block level development.
• Specify, architect and design low voltage and low power Mixed-Signal integrated circuits and work collaboratively with digital designers.
• Plan design work with constraints on performance, schedule and quality.
• Provide guidance to junior designers and layout engineers.
• Guidance to develop test plans for post-silicon characterization.
• Document all design work with review materials and detailed design descriptions.

Minimum QualificationsThe ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies.• Hands-on circuit design experience of SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc. for 28Gbps+ data rates.
• Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA) and modulator drivers.
• Experience with design of precision analog circuits like ADC/DACs.
• Experience with designing PAM4/NRZ links.
• Experience with Mixed signal design flow
• Experience with full-chip designs, ESDs and verification flows.
Preferred Qualifications
• Familiarity with Optical communications.
• Experience with 400G/800G/1.6T optical links.
• Experience with package/test setup design.

Experienced HireShift 1 (United States of America)US, California, Santa Clara
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 214,730.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

In this position, you will function as a senior technical member in the NPU architecture performance COE(center-of-excellence)

The role’s responsibilities include but are not limited to:

• Define performance model architecture and modeling flow to best reflect the interworking of NPU SW/HW.
• Implementing and testing performance models with systematic SW development practice.
• Conductperformance-and-poweranalysis of various neural network workloads.
• Utilize the performance data-driven flow to drive the NPU architecture definition.
• Collaborates with management, product owners, and project managers to evaluate feasibility of requirements and determine priorities for development.
• Performs pathfinding, surveys technologies, participates in standards committees, and presents at external and internal events.
• May interact with multiple technologists in the company to influence architectures and optimize/customize software offerings.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications could be obtained through a combination of schoolwork, classes, research, and/or relevant previous job and/or internship experiences.

Minimum Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Engineering, or Computer Science or related engineering field with 6+ years of relevant experience – OR – Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science or related engineering field with 4+ years of relevant experience – OR – PhD in Electrical Engineering, Computer Engineering/Computer Science with 2+ years of relevant experience, or related engineering field
• 6+ years of experience in two or more of the following:
  • Knowledge of computer architecture concepts such as pipelining, caching, parallel computing with SIMD/VLIW,multi-core/multi-threading,data precision, memory hierarchy
  • Understanding HW modeling concepts such as event-driven, concurrency, etc.
  • Knowledge of AI framework, AI models and basic neural computing operations.
  • Knowledge of data precision, floating point vs fixed point computing trade-offs.

Preferred Qualifications

• Experiences for object-oriented programming in C/C++ or Python. Capable of design class objects, data structure and API methods are required.
• Prior usage of event-driven modeling language (SC/C++/Python) and platforms
• Prior experience in architecture definition and/or mentoring junior engineers is highly desirable.

Experienced HireShift 1 (United States of America)US, California, Santa ClaraUS, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro, US, Oregon, Portland
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 168,100.00 USD - 299,040.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Role Overview:

The Senior Thermal Architect will lead thermal design and strategy for next-generation GPU, AI accelerators, and data center products. This role is critical to enabling high-performance computing at scale while meeting stringent thermal requirements. You will define thermal architecture across silicon, package, and platform levels, ensuring optimal thermal performance for products approaching multi-kilowatt levels:

Key Responsibilities:

• Define and deliver advanced packaging thermal solutions for advanced GPU/AI products
• Architect thermal strategies for 3DIC and advanced packaging technologies, including chiplets and heterogeneous integration.

• Develop analytical and experimental methods for thermal characterization and prediction.
• Drive co-optimization of thermal, electrical, and mechanical design across silicon, package, and system levels.

• Push the boundaries of thermal management to support Moore's Law progression.
• Evaluate and integrate emerging cooling technologies (e.g., liquid cooling, immersion cooling) for data center sustainability.

• Partner with silicon design, packaging, and platform teams to ensure thermal compliance and performance.
• Engage with external customers and ecosystem partners to align thermal solutions with product requirements.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Knowledge and/or experience listed below would be obtained through a combination of your school, work and/or classes and/or research and/or relevant previous job and/or internship experiences

Minimum Qualifications

• MS or PhD in Mechanical Engineering, Thermal Sciences, or related field.
• 10+ years in thermal design of semiconductor products
• Proven track record in thermal architecture and advanced packaging.
• Proficient in thermal simulation tools (e.g., CFD, FEA) and experimental validation.

Preferred Qualifications

• 10 + years experience in high-performance computing or data center products.
• Proven track record in GPU/AI thermal architecture and advanced packaging.
• Experience with rack-scale cooling solutions and liquid cooling technologies.
• Familiarity with AI/GPU performance trends and their thermal implications.
• Strong understanding of power delivery, energy efficiency, and cooling technologies.
• Ability to influence architecture decisions and drive innovation across global teams.

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 136,990.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:Experienced HireShift 1 (United States of America)US, California, Santa ClaraUS, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 213,640.00 USD - 301,610.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

The Applied Machine Learning group is responsible for innovation and development of end-to-end AI solutions, technology proof of concepts, and IP development of current and future ML workloads for Intel architecture and silicon serving consumer and corporate business requirements.

In this position, you will be responsible for research, modeling, prototyping, productizing of ML techniques, generating data insights and optimizations for Intel platforms.

Responsibilities include but are not limited to:

• Builds machine learning based products/solutions, which provide descriptive, diagnostic, predictive, or prescriptive models based on data.
• Uses or develops machine learning algorithms, such as supervised and unsupervised learning, deep learning, reinforcement learning, generative AI, large language model and others, to solve applied problems in various disciplines such as Data Analytics, Computer Vision, Natural Language Processing, Recommendation System, Graph Neural Network, Robotics, etc.
• Interacts with users to define requirements for breakthrough product/solutions.
• In either research environments or specific product environments, utilizes current programming methodologies to translate machine learning models and data processing methods into software.
• Completes programming, testing, debugging, documentation and/or deployment of the solution/products.
• Engineers big data computing frameworks, data modeling and other relevant software tools.
• You will play a key technical role for end-2-end machine learning and deep learning platform development based on various frameworks and hardware (such as CPU, GPU, accelerators).
• You will also be responsible for developing AI ML solutions and methodologies to bring the best performance, accuracy, efficiency, and ease-of-use to customers by working with internal and external partners.

The job scope may include but not limited to:

• End-2-end ML and DL platform component innovation and feature development in data ingestion, feature engineering, distributed training via data and model parallelization, hyper-parameter optimization, neural architecture search, model compression, quantization, distillation, and model serving.
• Algorithm and model development of advanced technologies in computer vision, natural language processing, large language model, recommendation, graph analytics, reinforcement learning, and other domains.
• Machine learning framework and workload performance profiling, optimization, insights generation for benchmark such as MLPerf as well as real-world customer use cases.
• Software and tools development in python, C++, and other languages as required.

Behavioral traits that we are looking for:

• Excellent communication skills.
• Willing to clearly communicate technical details and concept.

Qualifications:

Minimum qualifications,you must possess the below minimum qualifications to be initially considered for this position:

• Master´s degree with 4+ years or Ph.D. with 2+ years of experience in: Computer Engineering, Computer Science, Data Science, Software Engineering, Electronic Engineering, Physics, Mathematics, Aerospace engineering, applied mathematics, mechanical engineering, or related STEM disciplines

4+years of the following technical skills:

• Experience in deep learning frameworks such as PyTorch, TensorFlow, working on CPU / GPU / AI accelerators for ML/DL.
• Experience in GenAI frameworks such as transformers, PEFT, diffusers, TGI, TEI, vLLM or SGLang for both training finetuning and inference serving.
• Working with Performance optimization / tuning.
• Experience in computer vision, recommendation, natural language processing, or reinforcement learning.

Preferred qualificationsare in addition to the minimum requirements and are considered a plus factor in identifying top candidates:

• Proven track record of a leadership role in machine learning, deep learning research and applications demonstrated by patents, publications, product delivery, or other means.
• Experience on performance optimization for PyTorch framework, MLPerf benchmark and other SOTA workload.
• Distributed training, DeepSpeed, Torch DDP and FSDP, Ray SGD.
• Inference optimization such as quantization, sparsity, distillation.GenAI end-2-end workflow development and deployment for model serving, RAG and agent system.

Experienced HireShift 1 (United States of America)US, California, Santa Clara
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Key Responsibilities:

• Lead the co-design of silicon and package, focusing on DDR PHY and mixed signal IP integration for server SOCs.
• Design bump maps, floor plans, and manage area constraints for PHYs, collaborating closely with packaging technical experts.
• Conduct hands-onpackage extractionsand simulations(signal integrity, power integrity)
• Finalize bump-out, floor plan, and area decisions at the end of tech readiness phases.
• Interface with packaging teams on advanced technologies (e.g., C4 bumps, micro bumps, EMIB, hybrid bonding as needed).
• Focus on design, development, and architecture, not process or materials engineering.

Required Experience:

• Experience in both silicon design (preferably mixed signal/analog) and packaging co-design.
• Background in DDR, SOC, or similar high-speed interface development.
• Hands-on expertise with bump mapping, floor planning, and packaging constraints.
• Proven ability to collaborate across silicon and packaging teams, including risk assessment and simulation.
• Familiarity with advanced packaging technologies (hybrid bonding, EMIB, etc.) is a plus but not required.
• Individual contributor or principal engineer level preferred; management experience is not required.
• Experience at leading companies in advanced packaging and PHY design (e.g., Apple, Broadcom, Qualcomm, Micron, AMD, Nvidia).

Qualifications:

• Bachelors in electrical engineering, chemical engineering, mechanical engineering, material science or similar field (Master’s or Ph.D. preferred).
• 10+ years in silicon and packaging co-design

Experienced HireShift 1 (United States of America)US, California, FolsomUS, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

Job Description:

About the Role: We are seeking a highly experienced Senior Software Expert specializing in SoC Power and Performance Architecture to join our innovative team. In this pivotal role, you will leverage your expertise to enhance the power efficiency and performance of our System-on-Chip (SoC) designs. You will collaborate with cross-functional teams to ensure our SoCs achieve optimal performance and power efficiency, while identifying and implementing opportunities for improvement. You will also be setting simulation methodologies and driving those across the teams.

Key Responsibilities:
• Power and Performance Optimization: Lead and drive initiatives to optimize SoC power and performance through advanced software techniques, including firmware tuning, workload analysis, and architectural design modifications.
• Collaboration: Partner with architects, design engineers, validation teams, and marketing to deliver industry-leading SoC solutions, providing software insights and expertise.
• Pre-Silicon Planning: Define and implement detailed power and performance tools and methodologies in the pre-silicon phase, focusing on software architecture and design.
• DevOps Pipeline Establishment: Develop and establish DevOps pipelines for power, performance, and thermal architecture tools and methodologies, ensuring efficient and automated workflows.
• Simulation Technologies: Establish and implement simulation technologies and methodologies to predict and analyze power, performance, and thermal characteristics.
• Simulation Model Development: Develop and refine simulation models for power, performance, and thermal analysis, enabling accurate and predictive assessments of SoC designs.

Qualifications:

Minimum Qualifications:

• Bachelor's degree with 7+ years of experience or
• Master's degree with 5+ years of experience, or
• PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications:

• In-depth knowledge of CPU architecture, benchmarks, power management, and memory sub-system validation.
• Extensive experience in simulation development in the pre-RTL phase.
• Strong background in SW architecture and quality.
• Proficiency in developing simulation models for SoC.
• Advanced software development skills, including experience with scripting languages such as Python, C++.
• Deep understanding and experience with operating systems.
• Expertise in statistical data analysis and design of experiments.
• Familiarity with industry benchmarks, understanding the aspects of performance they measure, and conducting competitive analysis from previous generation products.

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.