Soc Director jobs at Intel in India, Bengaluru

The DFT Director's responsibilities include (but are not limited to):2. Drive DFT technical readiness (TR) and define DFT strategy to meet the Intel Manufacturing requirements
3. Work with the team to define DFT quality control/process for SoC execution predictability and high quality DFT delivery to achieve the first-time-right goals
4. Improve overall product cost by analyzing product requirement to balance DFT/Manufacturing requirements vs products' PPA and cost
5. Support critical post-Si debug and yield/Vmin analysis as required7. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environmentBachelors Degree in Electrical/Computer Engineering or related STEM degree plus 20+ years of industry experience in the following:
Expert in industry standard DFT (TAP/JTAG, MBIST, SCAN/ATPG)
Experienced in DFT productwith end-to-end DFT design and verification flow knowledge from DFT technical readiness (TR) to product PRQ support
Experienced with EDA tools such as ATPG tools, Siemens Tessent shell, VCS simulation and/or debug tools, Prime time and DFTC and/or similar tools
Understand the best known method to integrate IP from internal and/or external vendors, such as IO PHY and PLL
Experienced in DFT pattern generation flow, post-Si debug and yield analysis
Experienced HireShift 1 (India)India, BangaloreThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Job Description:

• Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
• Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
• Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.
• Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

• B.Tech. or M.Tech. inElectrical/ElectronicsEngineering with 8-12+ years' of experience.
• Key skills: Experience in all aspects of physical design flow in SOC using Synopsys and cadence tools.
• Experience in timing signoff, formal verification and low power static signoff.
• Experience in all aspects of clock distribution.
• Experience in deep submicron process technology nodes is strongly preferred.
• Solid understanding of power delivery and power plane distributions, power estimation and optimization in SOC.
• Solid understanding industry standard tools for synthesis, place and route and tape out flows.Solid understanding of physical design verification methods to debug LVS/DRC.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience.Related technical experience should be in/with: Silicon Design and/orPreferred Qualifications:Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies.The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.Experience in Xeon CPU Pre-Silicon or Post Silicon Validation.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orExperienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff include formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to fix violations for current and future product architecture.
• Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
• Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

BS/BTech degree with 8 years of experience, or MS/MTech degree with 6 years of experience, in Electronics Computer Engineering, or a related field.

• Preferred Qualifications:
• At least 7-13 years of experience in physical design using industry EDA tools.
• Experience in Python/Perl/TCL programming languages.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Come join Intel's Design Development Group organization as an SOC Verification engineering focused on Design for Debug (DFD). As a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites. You will also work closely with post-silicon validation SW teams on debug tool validation and silicon enabling. You will be pioneering new debug tools and flows, reviewing and publishing architectural specs and supporting next-generation silicon enabling on system platforms.Your responsibilities will include but not be limited to:

• Verification of Design for Debug features (e.g. low and high-bandwidth signal tracing and event triggering) using simulation, emulation, and/or FPGA.
• Creating test plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide.
• Learning Power Management, Memory and debug architecture and microarchitecture by debugging failures to the root cause.
• Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design.
• Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models.
• Developing debugging tools and software.

Minimum Qualifications:

• Candidate must have either a BE /ME / MTech or MS in Electronics, VLSI, Microelectronics, Computer Science or Electrical Engineering with 4-10 Years of experience.
• Extensive Pre-silicon Track record of driving debug tools enabling and validation, improvements and getting them adopted by others.
• Proven record of working across verification teams to solve problems.
• Expert of HW and SW Interaction and debug to root cause.
• Experience working across verification, architecture, SW, and design teams to resolve debug issues.
  Minimum 4 years of experience with writing verification plans and testcases to implement those validation plans.
• Minimum 4years of SOC Verification or Functional verification.
• Minimum 2yrs experience with Programming languages/Scripting: C, Perl, Python, Verilog and UNIX or Linux.
• Minimum 2yrs experience with SOC Architecture.
• Must have 4yrs+ experience with SOC Verification or Functional Verification.
• Must have 4yrs+ experience with validation or testing experience, especially in a silicon design team.

Preferred Qualifications

• Good to have 2yrs+ experience with industry standards such as JTAG, Tessent and Debug architecture.
• Good to have working experience on assertions, coverage and Formal verification

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

About the Role

We are seeking an exceptionally motivated and experienced Silicon Development Engineer to lead thearchitecture/micro-architecturedefinition and design of complex System-on-Chip (SoC) solutions. This role demands extensive understanding of SoC Architecture, Digital IP, and Network-on-Chip Interconnect design, coupled with significant pre/post-silicon debug expertise. The successful candidate will be instrumental in defining and implementing chassis architectures for advancedhigh-compute/performanceSoCs.

Key Responsibilities:

• Leadarchitecture/micro-architecturedefinition for advanced high performance SoCs, including chiplet-based designs supporting high throughput die to die coherency.
• Define and implement a scalable & high compute Chassis architecture for AI based consumer and server SoCs
• Drive micro-arch and design for high PPA solutions with optimised clock, reset, power for high compute SoC designs.
• Define end-to-end QoS solutions for multiple traffic class systems and implement low-latency, Head of Line blocking-free high throughput networks with complete freedom from interference
• Oversee SoC Chassis architecture, including Fabrics, SMMU & Access control
• Define Coresight compliant Debug and trace architecture for the chassis & SoC
• Work with design team to manage full-chip implementation of SoCs, encompassing Interconnect, SMMUs, Reset, Clocking, IO Mux, Debug-Trace, and High-Speed & Low speed IO Peripherals
• Work with Physical design teams to define the right SoC/Chassis partitioning, floor planning for a highly scalable SoC solution
• Drive project management, leading functional teams, and managing cross-functional multi-site projects.

Minimum Qualifications

BS in electrical engineer or computer science with 12+ years of experience

8+ Years of in silicon development engineering, with a strong focus on complex SoC Architecture.

5+ years of experience in experience in pre/post silicon debug.

5+ Years of experience with Memory & High-Speed interfacing

Deep understanding of Full chip System bus/fabric architecture (Coherent & Non-coherent).

Proven expertise in building SoCs with complex traffic class system with real time high throughput traffic management.

Strong background in Synthesis & Timing Analysis (Design Compiler/Primetime).

Experience with SOC Partitioning & Floor planning & strong awareness of technology nodes.

Preferred Qualifications

Strong understanding of latest DIE2DIE interfaces like UCIE & high-speed peripherals (PCIE) & Low speed peripherals (UART, SPI, CAN)

Solid knowledge of Multi-core infrastructure & IPC communication for efficient & performance SoC (looks good)

Proficiency with Simulation, Validation, and Signoff tools (IUS, Verdi, CDC, RDC, Lint).’’ (looks good)

Experience with 3nm chiplet-based SoC & chassis architecture.

Familiarity with UCIE based chiplet designs.

Hands-on experience with AMBA/CHI/UCIE/PCIE compliant High throughout interconnects.

Prior experience in leading microarchitecture and design forconsumer/wireless/automotive/ServerHPC SoCs.

Proven track record of defining and implementing low power, isolation & power management architectures.

Experience with third-party IP evaluation and liaison

Experienced HireShift 1 (India)India, BangaloreThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Defines, develops, and performs functional validation for integrated SoCs, focusing on validation of IP integration, interaction between IPs, and systemlevel features. Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met. Reviews proposed design changes to assess impact on validation plans, tasks, and timelines. Develops SoC validation methodologies, validation test plans, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis. Performs silicon debug to identify root causes and resolves all functional and triage failures for SoC issues. Tests interactions between various SoC features using validation infrastructure. Develops postsilicon validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing. Publishes SoC validation reports summarizing all validation activities performed, reviews results, and communicates to relevant teams. Works with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for SoC interfaces and to meet desired product specifications. Develops content to create or increase specific IP interactions using a variety of tools and techniques (including patching techniques using microcode, firmware, or custom OS builds). Engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (e.g., simulation, emulation, FPGAs) to ensure silicon readiness.
Qualifications:

• Bachelor's/Master's in Hardware Engineering /Electronics Engineering /Computer Engineering or Computer Science with minimum 6 years to 10 years (Domain Lead position) of related work experience.
• Candidate Must have high degree of Hardware architecture/ microarchitecture experience in CPU/SoC/Chipset/and one of the subsystems areas given below
• Must have [in any one or more domains]
• Deep understanding in one or more protocols from PCIe Express, USB3, DP, Bare metal
• Expertise hands on with programming languages C, C++, Python & Expert understanding Data Structures.
• Good To have Firmware development & validation experience
• Good to have Type C, Thunderbolt [TBT3/ USB4 and USB5] knowledge.
• Excellent written and oral communications and experience working in a cross functional team environment are essential.
• Good Team Player.
• Processes strong problem solving, analytical and debug skills.

Added advantage

• Good working knowledge in C++/Python SW programming for content development and scripting.
• Knowledge of IA/ARM core and system level Power Management architecture who familiar in PMC feature, Gate/Chip level power management transition state & etc.
• Understanding of System Reset related Validation expertise is a plus.
• Solid understanding of the Validation and Debug flows of a complex CPU Silicon
• Knowledge on Validation/ Debug Flows and overall SOC Architecture.
• Pre-silicon Design / Validation knowledge is a value added.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.